1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2014 Freescale Semiconductor, Inc.
8 #include <clock_legacy.h>
9 #include <fdt_support.h>
14 #include <asm/arch/immap_ls102xa.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/fsl_serdes.h>
17 #include <asm/arch/ls102xa_soc.h>
18 #include <asm/arch/ls102xa_devdis.h>
25 #include <fsl_devdis.h>
26 #include <fsl_validate.h>
28 #include "../common/sleep.h"
29 #include "../common/qixis.h"
30 #include "ls1021aqds_qixis.h"
35 #define PIN_MUX_SEL_CAN 0x03
36 #define PIN_MUX_SEL_IIC2 0xa0
37 #define PIN_MUX_SEL_RGMII 0x00
38 #define PIN_MUX_SEL_SAI 0x0c
39 #define PIN_MUX_SEL_SDHC 0x00
41 #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0x0f) | value)
42 #define SET_EC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
50 MUX_TYPE_SD_PC_SA_SG_SG,
51 MUX_TYPE_SD_PC_SA_PC_SG,
63 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
66 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
70 puts("Board: LS1021AQDS\n");
74 #elif CONFIG_QSPI_BOOT
77 sw = QIXIS_READ(brdcfg[0]);
78 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
81 printf("vBank: %d\n", sw);
89 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
92 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
93 printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n",
94 QIXIS_READ(id), QIXIS_READ(arch));
96 printf("FPGA: v%d (%s), build %d\n",
97 (int)QIXIS_READ(scver), qixis_read_tag(buf),
98 (int)qixis_read_minor());
104 unsigned long get_board_sys_clk(void)
106 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
108 switch (sysclk_conf & 0x0f) {
109 case QIXIS_SYSCLK_64:
111 case QIXIS_SYSCLK_83:
113 case QIXIS_SYSCLK_100:
115 case QIXIS_SYSCLK_125:
117 case QIXIS_SYSCLK_133:
119 case QIXIS_SYSCLK_150:
121 case QIXIS_SYSCLK_160:
123 case QIXIS_SYSCLK_166:
129 unsigned long get_board_ddr_clk(void)
131 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
133 switch ((ddrclk_conf & 0x30) >> 4) {
134 case QIXIS_DDRCLK_100:
136 case QIXIS_DDRCLK_125:
138 case QIXIS_DDRCLK_133:
144 int select_i2c_ch_pca9547(u8 ch, int bus_num)
147 #if CONFIG_IS_ENABLED(DM_I2C)
150 ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
153 printf("%s: Cannot find udev for a bus %d\n", __func__,
157 ret = dm_i2c_write(dev, 0, &ch, 1);
159 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
162 puts("PCA: failed to select proper channel\n");
172 * When resuming from deep sleep, the I2C channel may not be
173 * in the default channel. So, switch to the default channel
174 * before accessing DDR SPD.
176 * PCA9547(0x77) mount on I2C1 bus
178 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
179 return fsl_initdram();
182 int board_early_init_f(void)
184 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
186 #ifdef CONFIG_TSEC_ENET
187 /* clear BD & FR bits for BE BD's and frame data */
188 clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
191 #ifdef CONFIG_FSL_IFC
192 init_early_memctl_regs();
197 #if defined(CONFIG_DEEP_SLEEP)
199 fsl_dp_disable_console();
205 #ifdef CONFIG_SPL_BUILD
206 void board_init_f(ulong dummy)
208 #ifdef CONFIG_NAND_BOOT
209 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
213 * There is LS1 SoC issue where NOR, FPGA are inaccessible during
214 * NAND boot because IFC signals > IFC_AD7 are not enabled.
215 * This workaround changes RCW source to make all signals enabled.
217 porsr1 = in_be32(&gur->porsr1);
218 pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
219 DCFG_CCSR_PORSR1_RCW_SRC_I2C);
220 out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
225 memset(__bss_start, 0, __bss_end - __bss_start);
227 #ifdef CONFIG_FSL_IFC
228 init_early_memctl_regs();
233 #if defined(CONFIG_DEEP_SLEEP)
235 fsl_dp_disable_console();
238 preloader_console_init();
240 #ifdef CONFIG_SPL_I2C_SUPPORT
247 /* Allow OCRAM access permission as R/W */
248 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
249 enable_layerscape_ns_access();
252 board_init_r(NULL, 0);
256 void config_etseccm_source(int etsec_gtx_125_mux)
258 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
260 switch (etsec_gtx_125_mux) {
262 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE0_CLK125);
263 debug("etseccm set to GE0_CLK125\n");
267 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
268 debug("etseccm set to GE2_CLK125\n");
272 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE1_CLK125);
273 debug("etseccm set to GE1_CLK125\n");
277 printf("Error! trying to set etseccm to invalid value\n");
282 int config_board_mux(int ctrl_type)
286 reg12 = QIXIS_READ(brdcfg[12]);
287 reg14 = QIXIS_READ(brdcfg[14]);
291 config_etseccm_source(GE2_CLK125);
292 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN);
295 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2);
298 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII);
301 config_etseccm_source(GE2_CLK125);
302 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI);
305 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC);
307 case MUX_TYPE_SD_PCI4:
310 case MUX_TYPE_SD_PC_SA_SG_SG:
313 case MUX_TYPE_SD_PC_SA_PC_SG:
316 case MUX_TYPE_SD_PC_SG_SG:
320 printf("Wrong mux interface type\n");
324 QIXIS_WRITE(brdcfg[12], reg12);
325 QIXIS_WRITE(brdcfg[14], reg14);
330 int config_serdes_mux(void)
332 struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
335 cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
336 cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
340 config_board_mux(MUX_TYPE_SD_PCI4);
343 config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG);
346 config_board_mux(MUX_TYPE_SD_PC_SG_SG);
349 config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG);
352 printf("SRDS1 prtcl:0x%x\n", cfg);
359 #ifdef CONFIG_BOARD_LATE_INIT
360 int board_late_init(void)
362 #ifdef CONFIG_CHAIN_OF_TRUST
363 fsl_setenv_chain_of_trust();
370 int misc_init_r(void)
374 /* some signals can not enable simultaneous*/
376 if (hwconfig("sdhc"))
378 if (hwconfig("iic2"))
380 if (conflict_flag > 1) {
381 printf("WARNING: pin conflict !\n");
386 if (hwconfig("rgmii"))
392 if (conflict_flag > 1) {
393 printf("WARNING: pin conflict !\n");
398 config_board_mux(MUX_TYPE_CAN);
399 else if (hwconfig("rgmii"))
400 config_board_mux(MUX_TYPE_RGMII);
401 else if (hwconfig("sai"))
402 config_board_mux(MUX_TYPE_SAI);
404 if (hwconfig("iic2"))
405 config_board_mux(MUX_TYPE_IIC2);
406 else if (hwconfig("sdhc"))
407 config_board_mux(MUX_TYPE_SDHC);
409 #ifdef CONFIG_FSL_DEVICE_DISABLE
410 device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
412 #ifdef CONFIG_FSL_CAAM
420 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
423 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
424 erratum_a009942_check_cpo();
427 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
429 #ifndef CONFIG_SYS_FSL_NO_SERDES
434 ls102xa_smmu_stream_id_init();
443 #if defined(CONFIG_DEEP_SLEEP)
444 void board_sleep_prepare(void)
446 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
447 enable_layerscape_ns_access();
452 int ft_board_setup(void *blob, struct bd_info *bd)
454 ft_cpu_setup(blob, bd);
457 ft_pci_setup(blob, bd);
463 u8 flash_read8(void *addr)
465 return __raw_readb(addr + 1);
468 void flash_write16(u16 val, void *addr)
470 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
472 __raw_writew(shftval, addr);
475 u16 flash_read16(void *addr)
477 u16 val = __raw_readw(addr);
479 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);