1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2014 Freescale Semiconductor, Inc.
9 #include <asm/arch/immap_ls102xa.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/fsl_serdes.h>
12 #include <asm/arch/ls102xa_soc.h>
13 #include <asm/arch/ls102xa_devdis.h>
20 #include <fsl_devdis.h>
21 #include <fsl_validate.h>
23 #include "../common/sleep.h"
24 #include "../common/qixis.h"
25 #include "ls1021aqds_qixis.h"
30 #define PIN_MUX_SEL_CAN 0x03
31 #define PIN_MUX_SEL_IIC2 0xa0
32 #define PIN_MUX_SEL_RGMII 0x00
33 #define PIN_MUX_SEL_SAI 0x0c
34 #define PIN_MUX_SEL_SDHC 0x00
36 #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0x0f) | value)
37 #define SET_EC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
45 MUX_TYPE_SD_PC_SA_SG_SG,
46 MUX_TYPE_SD_PC_SA_PC_SG,
58 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
61 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
65 puts("Board: LS1021AQDS\n");
69 #elif CONFIG_QSPI_BOOT
72 sw = QIXIS_READ(brdcfg[0]);
73 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
76 printf("vBank: %d\n", sw);
84 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
87 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
88 printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n",
89 QIXIS_READ(id), QIXIS_READ(arch));
91 printf("FPGA: v%d (%s), build %d\n",
92 (int)QIXIS_READ(scver), qixis_read_tag(buf),
93 (int)qixis_read_minor());
99 unsigned long get_board_sys_clk(void)
101 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
103 switch (sysclk_conf & 0x0f) {
104 case QIXIS_SYSCLK_64:
106 case QIXIS_SYSCLK_83:
108 case QIXIS_SYSCLK_100:
110 case QIXIS_SYSCLK_125:
112 case QIXIS_SYSCLK_133:
114 case QIXIS_SYSCLK_150:
116 case QIXIS_SYSCLK_160:
118 case QIXIS_SYSCLK_166:
124 unsigned long get_board_ddr_clk(void)
126 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
128 switch ((ddrclk_conf & 0x30) >> 4) {
129 case QIXIS_DDRCLK_100:
131 case QIXIS_DDRCLK_125:
133 case QIXIS_DDRCLK_133:
139 int select_i2c_ch_pca9547(u8 ch)
143 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
145 puts("PCA: failed to select proper channel\n");
155 * When resuming from deep sleep, the I2C channel may not be
156 * in the default channel. So, switch to the default channel
157 * before accessing DDR SPD.
159 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
160 return fsl_initdram();
163 int board_early_init_f(void)
165 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
167 #ifdef CONFIG_TSEC_ENET
168 /* clear BD & FR bits for BE BD's and frame data */
169 clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
172 #ifdef CONFIG_FSL_IFC
173 init_early_memctl_regs();
178 #if defined(CONFIG_DEEP_SLEEP)
180 fsl_dp_disable_console();
186 #ifdef CONFIG_SPL_BUILD
187 void board_init_f(ulong dummy)
189 #ifdef CONFIG_NAND_BOOT
190 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
194 * There is LS1 SoC issue where NOR, FPGA are inaccessible during
195 * NAND boot because IFC signals > IFC_AD7 are not enabled.
196 * This workaround changes RCW source to make all signals enabled.
198 porsr1 = in_be32(&gur->porsr1);
199 pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
200 DCFG_CCSR_PORSR1_RCW_SRC_I2C);
201 out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
206 memset(__bss_start, 0, __bss_end - __bss_start);
208 #ifdef CONFIG_FSL_IFC
209 init_early_memctl_regs();
214 #if defined(CONFIG_DEEP_SLEEP)
216 fsl_dp_disable_console();
219 preloader_console_init();
221 #ifdef CONFIG_SPL_I2C_SUPPORT
228 /* Allow OCRAM access permission as R/W */
229 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
230 enable_layerscape_ns_access();
233 board_init_r(NULL, 0);
237 void config_etseccm_source(int etsec_gtx_125_mux)
239 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
241 switch (etsec_gtx_125_mux) {
243 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE0_CLK125);
244 debug("etseccm set to GE0_CLK125\n");
248 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
249 debug("etseccm set to GE2_CLK125\n");
253 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE1_CLK125);
254 debug("etseccm set to GE1_CLK125\n");
258 printf("Error! trying to set etseccm to invalid value\n");
263 int config_board_mux(int ctrl_type)
267 reg12 = QIXIS_READ(brdcfg[12]);
268 reg14 = QIXIS_READ(brdcfg[14]);
272 config_etseccm_source(GE2_CLK125);
273 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN);
276 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2);
279 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII);
282 config_etseccm_source(GE2_CLK125);
283 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI);
286 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC);
288 case MUX_TYPE_SD_PCI4:
291 case MUX_TYPE_SD_PC_SA_SG_SG:
294 case MUX_TYPE_SD_PC_SA_PC_SG:
297 case MUX_TYPE_SD_PC_SG_SG:
301 printf("Wrong mux interface type\n");
305 QIXIS_WRITE(brdcfg[12], reg12);
306 QIXIS_WRITE(brdcfg[14], reg14);
311 int config_serdes_mux(void)
313 struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
316 cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
317 cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
321 config_board_mux(MUX_TYPE_SD_PCI4);
324 config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG);
327 config_board_mux(MUX_TYPE_SD_PC_SG_SG);
330 config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG);
333 printf("SRDS1 prtcl:0x%x\n", cfg);
340 #ifdef CONFIG_BOARD_LATE_INIT
341 int board_late_init(void)
343 #ifdef CONFIG_CHAIN_OF_TRUST
344 fsl_setenv_chain_of_trust();
351 int misc_init_r(void)
355 /* some signals can not enable simultaneous*/
357 if (hwconfig("sdhc"))
359 if (hwconfig("iic2"))
361 if (conflict_flag > 1) {
362 printf("WARNING: pin conflict !\n");
367 if (hwconfig("rgmii"))
373 if (conflict_flag > 1) {
374 printf("WARNING: pin conflict !\n");
379 config_board_mux(MUX_TYPE_CAN);
380 else if (hwconfig("rgmii"))
381 config_board_mux(MUX_TYPE_RGMII);
382 else if (hwconfig("sai"))
383 config_board_mux(MUX_TYPE_SAI);
385 if (hwconfig("iic2"))
386 config_board_mux(MUX_TYPE_IIC2);
387 else if (hwconfig("sdhc"))
388 config_board_mux(MUX_TYPE_SDHC);
390 #ifdef CONFIG_FSL_DEVICE_DISABLE
391 device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
393 #ifdef CONFIG_FSL_CAAM
401 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
404 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
405 erratum_a009942_check_cpo();
408 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
410 #ifndef CONFIG_SYS_FSL_NO_SERDES
415 ls102xa_smmu_stream_id_init();
424 #if defined(CONFIG_DEEP_SLEEP)
425 void board_sleep_prepare(void)
427 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
428 enable_layerscape_ns_access();
433 int ft_board_setup(void *blob, bd_t *bd)
435 ft_cpu_setup(blob, bd);
438 ft_pci_setup(blob, bd);
444 u8 flash_read8(void *addr)
446 return __raw_readb(addr + 1);
449 void flash_write16(u16 val, void *addr)
451 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
453 __raw_writew(shftval, addr);
456 u16 flash_read16(void *addr)
458 u16 val = __raw_readw(addr);
460 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);