1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2014 Freescale Semiconductor, Inc.
8 #include <clock_legacy.h>
9 #include <fdt_support.h>
13 #include <asm/arch/immap_ls102xa.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/fsl_serdes.h>
16 #include <asm/arch/ls102xa_soc.h>
17 #include <asm/arch/ls102xa_devdis.h>
24 #include <fsl_devdis.h>
25 #include <fsl_validate.h>
27 #include "../common/sleep.h"
28 #include "../common/qixis.h"
29 #include "ls1021aqds_qixis.h"
34 #define PIN_MUX_SEL_CAN 0x03
35 #define PIN_MUX_SEL_IIC2 0xa0
36 #define PIN_MUX_SEL_RGMII 0x00
37 #define PIN_MUX_SEL_SAI 0x0c
38 #define PIN_MUX_SEL_SDHC 0x00
40 #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0x0f) | value)
41 #define SET_EC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
49 MUX_TYPE_SD_PC_SA_SG_SG,
50 MUX_TYPE_SD_PC_SA_PC_SG,
62 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
65 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
69 puts("Board: LS1021AQDS\n");
73 #elif CONFIG_QSPI_BOOT
76 sw = QIXIS_READ(brdcfg[0]);
77 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
80 printf("vBank: %d\n", sw);
88 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
91 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
92 printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n",
93 QIXIS_READ(id), QIXIS_READ(arch));
95 printf("FPGA: v%d (%s), build %d\n",
96 (int)QIXIS_READ(scver), qixis_read_tag(buf),
97 (int)qixis_read_minor());
103 unsigned long get_board_sys_clk(void)
105 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
107 switch (sysclk_conf & 0x0f) {
108 case QIXIS_SYSCLK_64:
110 case QIXIS_SYSCLK_83:
112 case QIXIS_SYSCLK_100:
114 case QIXIS_SYSCLK_125:
116 case QIXIS_SYSCLK_133:
118 case QIXIS_SYSCLK_150:
120 case QIXIS_SYSCLK_160:
122 case QIXIS_SYSCLK_166:
128 unsigned long get_board_ddr_clk(void)
130 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
132 switch ((ddrclk_conf & 0x30) >> 4) {
133 case QIXIS_DDRCLK_100:
135 case QIXIS_DDRCLK_125:
137 case QIXIS_DDRCLK_133:
143 int select_i2c_ch_pca9547(u8 ch, int bus_num)
149 ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
152 printf("%s: Cannot find udev for a bus %d\n", __func__,
156 ret = dm_i2c_write(dev, 0, &ch, 1);
158 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
161 puts("PCA: failed to select proper channel\n");
171 * When resuming from deep sleep, the I2C channel may not be
172 * in the default channel. So, switch to the default channel
173 * before accessing DDR SPD.
175 * PCA9547(0x77) mount on I2C1 bus
177 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
178 return fsl_initdram();
181 int board_early_init_f(void)
183 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
185 #ifdef CONFIG_TSEC_ENET
186 /* clear BD & FR bits for BE BD's and frame data */
187 clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
190 #ifdef CONFIG_FSL_IFC
191 init_early_memctl_regs();
196 #if defined(CONFIG_DEEP_SLEEP)
198 fsl_dp_disable_console();
204 #ifdef CONFIG_SPL_BUILD
205 void board_init_f(ulong dummy)
207 #ifdef CONFIG_NAND_BOOT
208 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
212 * There is LS1 SoC issue where NOR, FPGA are inaccessible during
213 * NAND boot because IFC signals > IFC_AD7 are not enabled.
214 * This workaround changes RCW source to make all signals enabled.
216 porsr1 = in_be32(&gur->porsr1);
217 pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
218 DCFG_CCSR_PORSR1_RCW_SRC_I2C);
219 out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
224 memset(__bss_start, 0, __bss_end - __bss_start);
226 #ifdef CONFIG_FSL_IFC
227 init_early_memctl_regs();
232 #if defined(CONFIG_DEEP_SLEEP)
234 fsl_dp_disable_console();
237 preloader_console_init();
239 #ifdef CONFIG_SPL_I2C_SUPPORT
246 /* Allow OCRAM access permission as R/W */
247 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
248 enable_layerscape_ns_access();
251 board_init_r(NULL, 0);
255 void config_etseccm_source(int etsec_gtx_125_mux)
257 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
259 switch (etsec_gtx_125_mux) {
261 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE0_CLK125);
262 debug("etseccm set to GE0_CLK125\n");
266 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
267 debug("etseccm set to GE2_CLK125\n");
271 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE1_CLK125);
272 debug("etseccm set to GE1_CLK125\n");
276 printf("Error! trying to set etseccm to invalid value\n");
281 int config_board_mux(int ctrl_type)
285 reg12 = QIXIS_READ(brdcfg[12]);
286 reg14 = QIXIS_READ(brdcfg[14]);
290 config_etseccm_source(GE2_CLK125);
291 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN);
294 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2);
297 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII);
300 config_etseccm_source(GE2_CLK125);
301 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI);
304 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC);
306 case MUX_TYPE_SD_PCI4:
309 case MUX_TYPE_SD_PC_SA_SG_SG:
312 case MUX_TYPE_SD_PC_SA_PC_SG:
315 case MUX_TYPE_SD_PC_SG_SG:
319 printf("Wrong mux interface type\n");
323 QIXIS_WRITE(brdcfg[12], reg12);
324 QIXIS_WRITE(brdcfg[14], reg14);
329 int config_serdes_mux(void)
331 struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
334 cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
335 cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
339 config_board_mux(MUX_TYPE_SD_PCI4);
342 config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG);
345 config_board_mux(MUX_TYPE_SD_PC_SG_SG);
348 config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG);
351 printf("SRDS1 prtcl:0x%x\n", cfg);
358 #ifdef CONFIG_BOARD_LATE_INIT
359 int board_late_init(void)
361 #ifdef CONFIG_CHAIN_OF_TRUST
362 fsl_setenv_chain_of_trust();
369 int misc_init_r(void)
373 /* some signals can not enable simultaneous*/
375 if (hwconfig("sdhc"))
377 if (hwconfig("iic2"))
379 if (conflict_flag > 1) {
380 printf("WARNING: pin conflict !\n");
385 if (hwconfig("rgmii"))
391 if (conflict_flag > 1) {
392 printf("WARNING: pin conflict !\n");
397 config_board_mux(MUX_TYPE_CAN);
398 else if (hwconfig("rgmii"))
399 config_board_mux(MUX_TYPE_RGMII);
400 else if (hwconfig("sai"))
401 config_board_mux(MUX_TYPE_SAI);
403 if (hwconfig("iic2"))
404 config_board_mux(MUX_TYPE_IIC2);
405 else if (hwconfig("sdhc"))
406 config_board_mux(MUX_TYPE_SDHC);
408 #ifdef CONFIG_FSL_DEVICE_DISABLE
409 device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
411 #ifdef CONFIG_FSL_CAAM
419 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
422 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
423 erratum_a009942_check_cpo();
426 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
428 #ifndef CONFIG_SYS_FSL_NO_SERDES
433 ls102xa_smmu_stream_id_init();
442 #if defined(CONFIG_DEEP_SLEEP)
443 void board_sleep_prepare(void)
445 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
446 enable_layerscape_ns_access();
451 int ft_board_setup(void *blob, bd_t *bd)
453 ft_cpu_setup(blob, bd);
456 ft_pci_setup(blob, bd);
462 u8 flash_read8(void *addr)
464 return __raw_readb(addr + 1);
467 void flash_write16(u16 val, void *addr)
469 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
471 __raw_writew(shftval, addr);
474 u16 flash_read16(void *addr)
476 u16 val = __raw_readw(addr);
478 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);