1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2016 Freescale Semiconductor, Inc.
8 #include <fdt_support.h>
11 #include <asm/cache.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/fsl_serdes.h>
16 #ifdef CONFIG_FSL_LS_PPA
17 #include <asm/arch/ppa.h>
19 #include <asm/arch/mmu.h>
20 #include <asm/arch/soc.h>
25 #include <fsl_esdhc.h>
26 #include <env_internal.h>
31 DECLARE_GLOBAL_DATA_PTR;
33 #define BOOT_FROM_UPPER_BANK 0x2
34 #define BOOT_FROM_LOWER_BANK 0x1
38 #ifdef CONFIG_TARGET_LS1012ARDB
42 puts("Board: LS1012ARDB ");
44 /* Initialize i2c early for Serial flash bank information */
45 #if defined(CONFIG_DM_I2C)
48 ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_IO_ADDR,
51 printf("%s: Cannot find udev for a bus %d\n", __func__,
55 ret = dm_i2c_read(dev, I2C_MUX_IO_1, &in1, 1);
56 #else /* Non DM I2C support - will be removed */
57 i2c_set_bus_num(bus_num);
58 ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &in1, 1);
61 printf("Error reading i2c boot information!\n");
62 return 0; /* Don't want to hang() on this error */
66 switch (in1 & SW_REV_MASK) {
93 printf(", boot from QSPI");
94 if ((in1 & SW_BOOT_MASK) == SW_BOOT_EMU)
96 else if ((in1 & SW_BOOT_MASK) == SW_BOOT_BANK1)
98 else if ((in1 & SW_BOOT_MASK) == SW_BOOT_BANK2)
104 puts("Board: LS1012A2G5RDB ");
109 #ifdef CONFIG_TFABOOT
112 gd->ram_size = tfa_get_dram_size();
114 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
121 #ifndef CONFIG_TFABOOT
122 static const struct fsl_mmdc_info mparam = {
123 0x05180000, /* mdctl */
124 0x00030035, /* mdpdc */
125 0x12554000, /* mdotc */
126 0xbabf7954, /* mdcfg0 */
127 0xdb328f64, /* mdcfg1 */
128 0x01ff00db, /* mdcfg2 */
129 0x00001680, /* mdmisc */
130 0x0f3c8000, /* mdref */
131 0x00002000, /* mdrwd */
132 0x00bf1023, /* mdor */
133 0x0000003f, /* mdasp */
134 0x0000022a, /* mpodtctrl */
135 0xa1390003, /* mpzqhwctrl */
141 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
142 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
143 /* This will break-before-make MMU for DDR */
144 update_early_mmu_table();
152 int board_early_init_f(void)
154 fsl_lsch2_early_init_f();
161 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
162 CONFIG_SYS_CCI400_OFFSET);
164 * Set CCI-400 control override register to enable barrier
167 if (current_el() == 3)
168 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
170 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
174 #ifdef CONFIG_ENV_IS_NOWHERE
175 gd->env_addr = (ulong)&default_environment[0];
178 #ifdef CONFIG_FSL_CAAM
182 #ifdef CONFIG_FSL_LS_PPA
188 #ifdef CONFIG_TARGET_LS1012ARDB
189 int esdhc_status_fixup(void *blob, const char *compat)
191 char esdhc1_path[] = "/soc/esdhc@1580000";
192 bool sdhc2_en = false;
195 int ret, bus_num = 0;
197 #if defined(CONFIG_DM_I2C)
200 ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_IO_ADDR,
203 printf("%s: Cannot find udev for a bus %d\n", __func__,
207 ret = dm_i2c_read(dev, I2C_MUX_IO_1, &io, 1);
209 i2c_set_bus_num(bus_num);
210 /* IO1[7:3] is the field of board revision info. */
211 ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &io, 1);
214 printf("Error reading i2c boot information!\n");
218 /* hwconfig method is used for RevD and later versions. */
219 if ((io & SW_REV_MASK) <= SW_REV_D) {
220 #ifdef CONFIG_HWCONFIG
221 if (hwconfig("esdhc1"))
226 * The I2C IO-expander for mux select is used to control
227 * the muxing of various onboard interfaces.
229 * IO0[3:2] indicates SDHC2 interface demultiplexer
232 * 01 - GPIO (to Arduino)
236 #if defined(CONFIG_DM_I2C)
237 ret = dm_i2c_read(dev, I2C_MUX_IO_0, &io, 1);
239 ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_0, 1, &io, 1);
242 printf("Error reading i2c boot information!\n");
246 mux_sdhc2 = (io & 0x0c) >> 2;
247 /* Enable SDHC2 only when use SDIO wifi and eMMC */
248 if (mux_sdhc2 == 2 || mux_sdhc2 == 0)
252 do_fixup_by_path(blob, esdhc1_path, "status", "okay",
255 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
256 sizeof("disabled"), 1);
261 int ft_board_setup(void *blob, bd_t *bd)
263 arch_fixup_fdt(blob);
265 ft_cpu_setup(blob, bd);
270 static int switch_to_bank1(void)
272 u8 data = 0xf4, chip_addr = 0x24, offset_addr = 0x03;
273 int ret, bus_num = 0;
275 #if defined(CONFIG_DM_I2C)
278 ret = i2c_get_chip_for_busnum(bus_num, chip_addr,
281 printf("%s: Cannot find udev for a bus %d\n", __func__,
286 * --------------------------------------------------------------------
287 * |bus |I2C address| Device | Notes |
288 * --------------------------------------------------------------------
289 * |I2C1|0x24, 0x25,| IO expander (CFG,| Provides 16bits of General |
290 * | |0x26 | RESET, and INT/ | Purpose parallel Input/Output|
291 * | | | KW41GPIO) - NXP | (GPIO) expansion for the |
292 * | | | PCAL9555AHF | I2C bus |
293 * ----- --------------------------------------------------------------
294 * - mount three IO expander(PCAL9555AHF) on I2C1
296 * PCAL9555A device address
298 * --------------------------------------
299 * | 0 | 1 | 0 | 0 | A2 | A1 | A0 | R/W |
300 * --------------------------------------
301 * | fixed | hardware selectable|
303 * Output port 1(Pinter register bits = 0x03)
306 * P1_0 <---> CFG_MUX_QSPI_S0
307 * P1_1 <---> CFG_MUX_QSPI_S1
308 * CFG_MUX_QSPI_S[1:0] = 0b00
310 * QSPI chip-select demultiplexer select
311 * ---------------------------------------------------------------------
312 * CFG_MUX_QSPI_S1|CFG_MUX_QSPI_S0| Values
313 * ---------------------------------------------------------------------
314 * 0 | 0 |CS routed to SPI memory bank1(default)
315 * ---------------------------------------------------------------------
316 * 0 | 1 |CS routed to SPI memory bank2
317 * ---------------------------------------------------------------------
320 ret = dm_i2c_write(dev, offset_addr, &data, 1);
321 #else /* Non DM I2C support - will be removed */
322 i2c_set_bus_num(bus_num);
323 ret = i2c_write(chip_addr, offset_addr, 1, &data, 1);
327 printf("i2c write error to chip : %u, addr : %u, data : %u\n",
328 chip_addr, offset_addr, data);
334 static int switch_to_bank2(void)
336 u8 data[2] = {0xfc, 0xf5}, offset_addr[2] = {0x7, 0x3};
338 int ret, i, bus_num = 0;
340 #if defined(CONFIG_DM_I2C)
343 ret = i2c_get_chip_for_busnum(bus_num, chip_addr,
346 printf("%s: Cannot find udev for a bus %d\n", __func__,
350 #else /* Non DM I2C support - will be removed */
351 i2c_set_bus_num(bus_num);
355 * 1th step: config port 1
356 * - the port 1 pin is enabled as an output
357 * 2th step: output port 1
358 * - P1_[7:0] output 0xf5,
359 * then CFG_MUX_QSPI_S[1:0] equal to 0b01,
360 * CS routed to SPI memory bank2
362 for (i = 0; i < sizeof(data); i++) {
363 #if defined(CONFIG_DM_I2C)
364 ret = dm_i2c_write(dev, offset_addr[i], &data[i], 1);
365 #else /* Non DM I2C support - will be removed */
366 ret = i2c_write(chip_addr, offset_addr[i], 1, &data[i], 1);
369 printf("i2c write error to chip : %u, addr : %u, data : %u\n",
370 chip_addr, offset_addr[i], data[i]);
379 static int convert_flash_bank(int bank)
384 case BOOT_FROM_UPPER_BANK:
385 ret = switch_to_bank2();
387 case BOOT_FROM_LOWER_BANK:
388 ret = switch_to_bank1();
398 static int flash_bank_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
402 return CMD_RET_USAGE;
403 if (strcmp(argv[1], "1") == 0)
404 convert_flash_bank(BOOT_FROM_LOWER_BANK);
405 else if (strcmp(argv[1], "2") == 0)
406 convert_flash_bank(BOOT_FROM_UPPER_BANK);
408 return CMD_RET_USAGE;
414 boot_bank, 2, 0, flash_bank_cmd,
415 "Flash bank Selection Control",
416 "bank[1-lower bank/2-upper bank] (e.g. boot_bank 1)"