1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2016 Freescale Semiconductor, Inc.
8 #include <fdt_support.h>
11 #include <asm/cache.h>
13 #include <asm/global_data.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/fsl_serdes.h>
17 #ifdef CONFIG_FSL_LS_PPA
18 #include <asm/arch/ppa.h>
20 #include <asm/arch/mmu.h>
21 #include <asm/arch/soc.h>
26 #include <fsl_esdhc.h>
27 #include <env_internal.h>
32 DECLARE_GLOBAL_DATA_PTR;
34 #define BOOT_FROM_UPPER_BANK 0x2
35 #define BOOT_FROM_LOWER_BANK 0x1
39 #ifdef CONFIG_TARGET_LS1012ARDB
43 puts("Board: LS1012ARDB ");
45 /* Initialize i2c early for Serial flash bank information */
46 #if CONFIG_IS_ENABLED(DM_I2C)
49 ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_IO_ADDR,
52 printf("%s: Cannot find udev for a bus %d\n", __func__,
56 ret = dm_i2c_read(dev, I2C_MUX_IO_1, &in1, 1);
57 #else /* Non DM I2C support - will be removed */
58 i2c_set_bus_num(bus_num);
59 ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &in1, 1);
62 printf("Error reading i2c boot information!\n");
63 return 0; /* Don't want to hang() on this error */
67 switch (in1 & SW_REV_MASK) {
94 printf(", boot from QSPI");
95 if ((in1 & SW_BOOT_MASK) == SW_BOOT_EMU)
97 else if ((in1 & SW_BOOT_MASK) == SW_BOOT_BANK1)
99 else if ((in1 & SW_BOOT_MASK) == SW_BOOT_BANK2)
105 puts("Board: LS1012A2G5RDB ");
110 #ifdef CONFIG_TFABOOT
113 gd->ram_size = tfa_get_dram_size();
115 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
122 #ifndef CONFIG_TFABOOT
123 static const struct fsl_mmdc_info mparam = {
124 0x05180000, /* mdctl */
125 0x00030035, /* mdpdc */
126 0x12554000, /* mdotc */
127 0xbabf7954, /* mdcfg0 */
128 0xdb328f64, /* mdcfg1 */
129 0x01ff00db, /* mdcfg2 */
130 0x00001680, /* mdmisc */
131 0x0f3c8000, /* mdref */
132 0x00002000, /* mdrwd */
133 0x00bf1023, /* mdor */
134 0x0000003f, /* mdasp */
135 0x0000022a, /* mpodtctrl */
136 0xa1390003, /* mpzqhwctrl */
142 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
143 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
144 /* This will break-before-make MMU for DDR */
145 update_early_mmu_table();
153 int board_early_init_f(void)
155 fsl_lsch2_early_init_f();
162 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
163 CONFIG_SYS_CCI400_OFFSET);
165 * Set CCI-400 control override register to enable barrier
168 if (current_el() == 3)
169 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
171 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
175 #ifdef CONFIG_ENV_IS_NOWHERE
176 gd->env_addr = (ulong)&default_environment[0];
179 #ifdef CONFIG_FSL_CAAM
183 #ifdef CONFIG_FSL_LS_PPA
189 #ifdef CONFIG_TARGET_LS1012ARDB
190 int esdhc_status_fixup(void *blob, const char *compat)
192 char esdhc1_path[] = "/soc/esdhc@1580000";
193 bool sdhc2_en = false;
196 int ret, bus_num = 0;
198 #if CONFIG_IS_ENABLED(DM_I2C)
201 ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_IO_ADDR,
204 printf("%s: Cannot find udev for a bus %d\n", __func__,
208 ret = dm_i2c_read(dev, I2C_MUX_IO_1, &io, 1);
210 i2c_set_bus_num(bus_num);
211 /* IO1[7:3] is the field of board revision info. */
212 ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &io, 1);
215 printf("Error reading i2c boot information!\n");
219 /* hwconfig method is used for RevD and later versions. */
220 if ((io & SW_REV_MASK) <= SW_REV_D) {
221 #ifdef CONFIG_HWCONFIG
222 if (hwconfig("esdhc1"))
227 * The I2C IO-expander for mux select is used to control
228 * the muxing of various onboard interfaces.
230 * IO0[3:2] indicates SDHC2 interface demultiplexer
233 * 01 - GPIO (to Arduino)
237 #if CONFIG_IS_ENABLED(DM_I2C)
238 ret = dm_i2c_read(dev, I2C_MUX_IO_0, &io, 1);
240 ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_0, 1, &io, 1);
243 printf("Error reading i2c boot information!\n");
247 mux_sdhc2 = (io & 0x0c) >> 2;
248 /* Enable SDHC2 only when use SDIO wifi and eMMC */
249 if (mux_sdhc2 == 2 || mux_sdhc2 == 0)
253 do_fixup_by_path(blob, esdhc1_path, "status", "okay",
256 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
257 sizeof("disabled"), 1);
262 int ft_board_setup(void *blob, struct bd_info *bd)
264 arch_fixup_fdt(blob);
266 ft_cpu_setup(blob, bd);
271 static int switch_to_bank1(void)
273 u8 data = 0xf4, chip_addr = 0x24, offset_addr = 0x03;
274 int ret, bus_num = 0;
276 #if CONFIG_IS_ENABLED(DM_I2C)
279 ret = i2c_get_chip_for_busnum(bus_num, chip_addr,
282 printf("%s: Cannot find udev for a bus %d\n", __func__,
287 * --------------------------------------------------------------------
288 * |bus |I2C address| Device | Notes |
289 * --------------------------------------------------------------------
290 * |I2C1|0x24, 0x25,| IO expander (CFG,| Provides 16bits of General |
291 * | |0x26 | RESET, and INT/ | Purpose parallel Input/Output|
292 * | | | KW41GPIO) - NXP | (GPIO) expansion for the |
293 * | | | PCAL9555AHF | I2C bus |
294 * ----- --------------------------------------------------------------
295 * - mount three IO expander(PCAL9555AHF) on I2C1
297 * PCAL9555A device address
299 * --------------------------------------
300 * | 0 | 1 | 0 | 0 | A2 | A1 | A0 | R/W |
301 * --------------------------------------
302 * | fixed | hardware selectable|
304 * Output port 1(Pinter register bits = 0x03)
307 * P1_0 <---> CFG_MUX_QSPI_S0
308 * P1_1 <---> CFG_MUX_QSPI_S1
309 * CFG_MUX_QSPI_S[1:0] = 0b00
311 * QSPI chip-select demultiplexer select
312 * ---------------------------------------------------------------------
313 * CFG_MUX_QSPI_S1|CFG_MUX_QSPI_S0| Values
314 * ---------------------------------------------------------------------
315 * 0 | 0 |CS routed to SPI memory bank1(default)
316 * ---------------------------------------------------------------------
317 * 0 | 1 |CS routed to SPI memory bank2
318 * ---------------------------------------------------------------------
321 ret = dm_i2c_write(dev, offset_addr, &data, 1);
322 #else /* Non DM I2C support - will be removed */
323 i2c_set_bus_num(bus_num);
324 ret = i2c_write(chip_addr, offset_addr, 1, &data, 1);
328 printf("i2c write error to chip : %u, addr : %u, data : %u\n",
329 chip_addr, offset_addr, data);
335 static int switch_to_bank2(void)
337 u8 data[2] = {0xfc, 0xf5}, offset_addr[2] = {0x7, 0x3};
339 int ret, i, bus_num = 0;
341 #if CONFIG_IS_ENABLED(DM_I2C)
344 ret = i2c_get_chip_for_busnum(bus_num, chip_addr,
347 printf("%s: Cannot find udev for a bus %d\n", __func__,
351 #else /* Non DM I2C support - will be removed */
352 i2c_set_bus_num(bus_num);
356 * 1th step: config port 1
357 * - the port 1 pin is enabled as an output
358 * 2th step: output port 1
359 * - P1_[7:0] output 0xf5,
360 * then CFG_MUX_QSPI_S[1:0] equal to 0b01,
361 * CS routed to SPI memory bank2
363 for (i = 0; i < sizeof(data); i++) {
364 #if CONFIG_IS_ENABLED(DM_I2C)
365 ret = dm_i2c_write(dev, offset_addr[i], &data[i], 1);
366 #else /* Non DM I2C support - will be removed */
367 ret = i2c_write(chip_addr, offset_addr[i], 1, &data[i], 1);
370 printf("i2c write error to chip : %u, addr : %u, data : %u\n",
371 chip_addr, offset_addr[i], data[i]);
380 static int convert_flash_bank(int bank)
385 case BOOT_FROM_UPPER_BANK:
386 ret = switch_to_bank2();
388 case BOOT_FROM_LOWER_BANK:
389 ret = switch_to_bank1();
399 static int flash_bank_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
403 return CMD_RET_USAGE;
404 if (strcmp(argv[1], "1") == 0)
405 convert_flash_bank(BOOT_FROM_LOWER_BANK);
406 else if (strcmp(argv[1], "2") == 0)
407 convert_flash_bank(BOOT_FROM_UPPER_BANK);
409 return CMD_RET_USAGE;
415 boot_bank, 2, 0, flash_bank_cmd,
416 "Flash bank Selection Control",
417 "bank[1-lower bank/2-upper bank] (e.g. boot_bank 1)"