1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2016 Freescale Semiconductor, Inc.
9 #include <fdt_support.h>
10 #include <asm/cache.h>
12 #include <asm/global_data.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/fsl_serdes.h>
16 #ifdef CONFIG_FSL_LS_PPA
17 #include <asm/arch/ppa.h>
19 #include <asm/arch/fdt.h>
20 #include <asm/arch/mmu.h>
21 #include <asm/arch/soc.h>
25 #include <env_internal.h>
28 #include <fsl_esdhc.h>
32 #include "../common/qixis.h"
33 #include "ls1012aqds_qixis.h"
34 #include "ls1012aqds_pfe.h"
35 #include <net/pfe_eth/pfe/pfe_hw.h>
37 DECLARE_GLOBAL_DATA_PTR;
44 sw = QIXIS_READ(arch);
45 printf("Board Arch: V%d, ", sw >> 4);
46 printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
48 sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
50 if (sw & QIXIS_LBMAP_ALTBANK)
55 printf("FPGA: v%d (%s), build %d",
56 (int)QIXIS_READ(scver), qixis_read_tag(buf),
57 (int)qixis_read_minor());
59 /* the timestamp string contains "\n" at the end */
60 printf(" on %s", qixis_read_time(buf));
67 gd->ram_size = tfa_get_dram_size();
69 gd->ram_size = CFG_SYS_SDRAM_SIZE;
76 static const struct fsl_mmdc_info mparam = {
77 0x05180000, /* mdctl */
78 0x00030035, /* mdpdc */
79 0x12554000, /* mdotc */
80 0xbabf7954, /* mdcfg0 */
81 0xdb328f64, /* mdcfg1 */
82 0x01ff00db, /* mdcfg2 */
83 0x00001680, /* mdmisc */
84 0x0f3c8000, /* mdref */
85 0x00002000, /* mdrwd */
86 0x00bf1023, /* mdor */
87 0x0000003f, /* mdasp */
88 0x0000022a, /* mpodtctrl */
89 0xa1390003, /* mpzqhwctrl */
93 gd->ram_size = CFG_SYS_SDRAM_SIZE;
94 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
95 /* This will break-before-make MMU for DDR */
96 update_early_mmu_table();
103 int board_early_init_f(void)
105 fsl_lsch2_early_init_f();
110 #ifdef CONFIG_MISC_INIT_R
111 int misc_init_r(void)
113 u8 mux_sdhc_cd = 0x80;
116 #if CONFIG_IS_ENABLED(DM_I2C)
120 ret = i2c_get_chip_for_busnum(bus_num, CONFIG_SYS_I2C_FPGA_ADDR,
123 printf("%s: Cannot find udev for a bus %d\n", __func__,
127 dm_i2c_write(dev, 0x5a, &mux_sdhc_cd, 1);
129 i2c_set_bus_num(bus_num);
131 i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1);
140 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
141 CONFIG_SYS_CCI400_OFFSET);
143 /* Set CCI-400 control override register to enable barrier
145 if (current_el() == 3)
146 out_le32(&cci->ctrl_ord,
147 CCI400_CTRLORD_EN_BARRIER);
149 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
153 #ifdef CONFIG_FSL_LS_PPA
159 #ifdef CONFIG_FSL_PFE
160 void board_quiesce_devices(void)
162 pfe_command_stop(0, NULL);
166 int esdhc_status_fixup(void *blob, const char *compat)
168 char esdhc0_path[] = "/soc/esdhc@1560000";
169 char esdhc1_path[] = "/soc/esdhc@1580000";
172 do_fixup_by_path(blob, esdhc0_path, "status", "okay",
176 * The Presence Detect 2 register detects the installation
177 * of cards in various PCI Express or SGMII slots.
179 * STAT_PRS2[7:5]: Specifies the type of card installed in the
180 * SDHC2 Adapter slot. 0b111 indicates no adapter is installed.
182 card_id = (QIXIS_READ(present2) & 0xe0) >> 5;
184 /* If no adapter is installed in SDHC2, disable SDHC2 */
186 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
187 sizeof("disabled"), 1);
189 do_fixup_by_path(blob, esdhc1_path, "status", "okay",
194 static int pfe_set_properties(void *set_blob, struct pfe_prop_val prop_val,
195 char *enet_path, char *mdio_path)
197 do_fixup_by_path(set_blob, enet_path, "fsl,gemac-bus-id",
198 &prop_val.busid, PFE_PROP_LEN, 1);
199 do_fixup_by_path(set_blob, enet_path, "fsl,gemac-phy-id",
200 &prop_val.phyid, PFE_PROP_LEN, 1);
201 do_fixup_by_path(set_blob, enet_path, "fsl,mdio-mux-val",
202 &prop_val.mux_val, PFE_PROP_LEN, 1);
203 do_fixup_by_path(set_blob, enet_path, "phy-mode",
204 prop_val.phy_mode, strlen(prop_val.phy_mode) + 1, 1);
205 do_fixup_by_path(set_blob, mdio_path, "fsl,mdio-phy-mask",
206 &prop_val.phy_mask, PFE_PROP_LEN, 1);
210 static void fdt_fsl_fixup_of_pfe(void *blob)
213 struct pfe_prop_val prop_val;
216 struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
217 unsigned int srds_s1 = in_be32(&gur->rcwsr[4]) &
218 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
219 srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
221 for (i = 0; i < NUM_ETH_NODE; i++) {
223 case SERDES_1_G_PROTOCOL:
225 prop_val.busid = cpu_to_fdt32(
227 prop_val.phyid = cpu_to_fdt32(
229 prop_val.mux_val = cpu_to_fdt32(
231 prop_val.phy_mask = cpu_to_fdt32(
232 ETH_1G_MDIO_PHY_MASK);
233 prop_val.phy_mode = "sgmii";
234 pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
237 prop_val.busid = cpu_to_fdt32(
239 prop_val.phyid = cpu_to_fdt32(
241 prop_val.mux_val = cpu_to_fdt32(
243 prop_val.phy_mask = cpu_to_fdt32(
244 ETH_1G_MDIO_PHY_MASK);
245 prop_val.phy_mode = "rgmii";
246 pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
250 case SERDES_2_5_G_PROTOCOL:
252 prop_val.busid = cpu_to_fdt32(
254 prop_val.phyid = cpu_to_fdt32(
256 prop_val.mux_val = cpu_to_fdt32(
257 ETH_1_2_5G_MDIO_MUX);
258 prop_val.phy_mask = cpu_to_fdt32(
259 ETH_2_5G_MDIO_PHY_MASK);
260 prop_val.phy_mode = "2500base-x";
261 pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
264 prop_val.busid = cpu_to_fdt32(
266 prop_val.phyid = cpu_to_fdt32(
268 prop_val.mux_val = cpu_to_fdt32(
269 ETH_2_2_5G_MDIO_MUX);
270 prop_val.phy_mask = cpu_to_fdt32(
271 ETH_2_5G_MDIO_PHY_MASK);
272 prop_val.phy_mode = "2500base-x";
273 pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
278 printf("serdes:[%d]\n", srds_s1);
283 #ifdef CONFIG_OF_BOARD_SETUP
284 int ft_board_setup(void *blob, struct bd_info *bd)
286 arch_fixup_fdt(blob);
288 ft_cpu_setup(blob, bd);
289 fdt_fsl_fixup_of_pfe(blob);