board/freescale/ls1012aqds/ls1012aqds.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2016 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <i2c.h>
   8 #include <fdt_support.h>
   9 #include <asm/cache.h>
  10 #include <init.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/fsl_serdes.h>
  14 #ifdef CONFIG_FSL_LS_PPA
  15 #include <asm/arch/ppa.h>
  16 #endif
  17 #include <asm/arch/fdt.h>
  18 #include <asm/arch/mmu.h>
  19 #include <asm/arch/soc.h>
  20 #include <ahci.h>
  21 #include <hwconfig.h>
  22 #include <mmc.h>
  23 #include <env_internal.h>
  24 #include <scsi.h>
  25 #include <fm_eth.h>
  26 #include <fsl_esdhc.h>
  27 #include <fsl_mmdc.h>
  28 #include <spl.h>
  29 #include <netdev.h>
  30 #include <fsl_sec.h>
  31 #include "../common/qixis.h"
  32 #include "ls1012aqds_qixis.h"
  33 #include "ls1012aqds_pfe.h"
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 int checkboard(void)
  38 {
  39         char buf[64];
  40         u8 sw;
  41
  42         sw = QIXIS_READ(arch);
  43         printf("Board Arch: V%d, ", sw >> 4);
  44         printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
  45
  46         sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
  47
  48         if (sw & QIXIS_LBMAP_ALTBANK)
  49                 printf("flash: 2\n");
  50         else
  51                 printf("flash: 1\n");
  52
  53         printf("FPGA: v%d (%s), build %d",
  54                (int)QIXIS_READ(scver), qixis_read_tag(buf),
  55                (int)qixis_read_minor());
  56
  57         /* the timestamp string contains "\n" at the end */
  58         printf(" on %s", qixis_read_time(buf));
  59         return 0;
  60 }
  61
  62 #ifdef CONFIG_TFABOOT
  63 int dram_init(void)
  64 {
  65         gd->ram_size = tfa_get_dram_size();
  66         if (!gd->ram_size)
  67                 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
  68
  69         return 0;
  70 }
  71 #else
  72 int dram_init(void)
  73 {
  74         static const struct fsl_mmdc_info mparam = {
  75                 0x05180000,     /* mdctl */
  76                 0x00030035,     /* mdpdc */
  77                 0x12554000,     /* mdotc */
  78                 0xbabf7954,     /* mdcfg0 */
  79                 0xdb328f64,     /* mdcfg1 */
  80                 0x01ff00db,     /* mdcfg2 */
  81                 0x00001680,     /* mdmisc */
  82                 0x0f3c8000,     /* mdref */
  83                 0x00002000,     /* mdrwd */
  84                 0x00bf1023,     /* mdor */
  85                 0x0000003f,     /* mdasp */
  86                 0x0000022a,     /* mpodtctrl */
  87                 0xa1390003,     /* mpzqhwctrl */
  88         };
  89
  90         mmdc_init(&mparam);
  91         gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
  92 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
  93         /* This will break-before-make MMU for DDR */
  94         update_early_mmu_table();
  95 #endif
  96
  97         return 0;
  98 }
  99 #endif
 100
 101 int board_early_init_f(void)
 102 {
 103         fsl_lsch2_early_init_f();
 104
 105         return 0;
 106 }
 107
 108 #ifdef CONFIG_MISC_INIT_R
 109 int misc_init_r(void)
 110 {
 111         u8 mux_sdhc_cd = 0x80;
 112         int bus_num = 0;
 113
 114 #ifdef CONFIG_DM_I2C
 115         struct udevice *dev;
 116         int ret;
 117
 118         ret = i2c_get_chip_for_busnum(bus_num, CONFIG_SYS_I2C_FPGA_ADDR,
 119                                       1, &dev);
 120         if (ret) {
 121                 printf("%s: Cannot find udev for a bus %d\n", __func__,
 122                        bus_num);
 123                 return ret;
 124         }
 125         dm_i2c_write(dev, 0x5a, &mux_sdhc_cd, 1);
 126 #else
 127         i2c_set_bus_num(bus_num);
 128
 129         i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1);
 130 #endif
 131
 132         return 0;
 133 }
 134 #endif
 135
 136 int board_init(void)
 137 {
 138         struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
 139                                    CONFIG_SYS_CCI400_OFFSET);
 140
 141         /* Set CCI-400 control override register to enable barrier
 142          * transaction */
 143         if (current_el() == 3)
 144                 out_le32(&cci->ctrl_ord,
 145                          CCI400_CTRLORD_EN_BARRIER);
 146
 147 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
 148         erratum_a010315();
 149 #endif
 150
 151 #ifdef CONFIG_ENV_IS_NOWHERE
 152         gd->env_addr = (ulong)&default_environment[0];
 153 #endif
 154
 155 #ifdef CONFIG_FSL_CAAM
 156         sec_init();
 157 #endif
 158
 159 #ifdef CONFIG_FSL_LS_PPA
 160         ppa_init();
 161 #endif
 162         return 0;
 163 }
 164
 165 int esdhc_status_fixup(void *blob, const char *compat)
 166 {
 167         char esdhc0_path[] = "/soc/esdhc@1560000";
 168         char esdhc1_path[] = "/soc/esdhc@1580000";
 169         u8 card_id;
 170
 171         do_fixup_by_path(blob, esdhc0_path, "status", "okay",
 172                          sizeof("okay"), 1);
 173
 174         /*
 175          * The Presence Detect 2 register detects the installation
 176          * of cards in various PCI Express or SGMII slots.
 177          *
 178          * STAT_PRS2[7:5]: Specifies the type of card installed in the
 179          * SDHC2 Adapter slot. 0b111 indicates no adapter is installed.
 180          */
 181         card_id = (QIXIS_READ(present2) & 0xe0) >> 5;
 182
 183         /* If no adapter is installed in SDHC2, disable SDHC2 */
 184         if (card_id == 0x7)
 185                 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
 186                                  sizeof("disabled"), 1);
 187         else
 188                 do_fixup_by_path(blob, esdhc1_path, "status", "okay",
 189                                  sizeof("okay"), 1);
 190         return 0;
 191 }
 192
 193 static int pfe_set_properties(void *set_blob, struct pfe_prop_val prop_val,
 194                               char *enet_path, char *mdio_path)
 195 {
 196         do_fixup_by_path(set_blob, enet_path, "fsl,gemac-bus-id",
 197                          &prop_val.busid, PFE_PROP_LEN, 1);
 198         do_fixup_by_path(set_blob, enet_path, "fsl,gemac-phy-id",
 199                          &prop_val.phyid, PFE_PROP_LEN, 1);
 200         do_fixup_by_path(set_blob, enet_path, "fsl,mdio-mux-val",
 201                          &prop_val.mux_val, PFE_PROP_LEN, 1);
 202         do_fixup_by_path(set_blob, enet_path, "phy-mode",
 203                          prop_val.phy_mode, strlen(prop_val.phy_mode) + 1, 1);
 204         do_fixup_by_path(set_blob, mdio_path, "fsl,mdio-phy-mask",
 205                          &prop_val.phy_mask, PFE_PROP_LEN, 1);
 206         return 0;
 207 }
 208
 209 static void fdt_fsl_fixup_of_pfe(void *blob)
 210 {
 211         int i = 0;
 212         struct pfe_prop_val prop_val;
 213         void *l_blob = blob;
 214
 215         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 216         unsigned int srds_s1 = in_be32(&gur->rcwsr[4]) &
 217                 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
 218         srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
 219
 220         for (i = 0; i < NUM_ETH_NODE; i++) {
 221                 switch (srds_s1) {
 222                 case SERDES_1_G_PROTOCOL:
 223                         if (i == 0) {
 224                                 prop_val.busid = cpu_to_fdt32(
 225                                                 ETH_1_1G_BUS_ID);
 226                                 prop_val.phyid = cpu_to_fdt32(
 227                                                 ETH_1_1G_PHY_ID);
 228                                 prop_val.mux_val = cpu_to_fdt32(
 229                                                 ETH_1_1G_MDIO_MUX);
 230                                 prop_val.phy_mask = cpu_to_fdt32(
 231                                                 ETH_1G_MDIO_PHY_MASK);
 232                                 prop_val.phy_mode = "sgmii";
 233                                 pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
 234                                                    ETH_1_MDIO);
 235                         } else {
 236                                 prop_val.busid = cpu_to_fdt32(
 237                                                 ETH_2_1G_BUS_ID);
 238                                 prop_val.phyid = cpu_to_fdt32(
 239                                                 ETH_2_1G_PHY_ID);
 240                                 prop_val.mux_val = cpu_to_fdt32(
 241                                                 ETH_2_1G_MDIO_MUX);
 242                                 prop_val.phy_mask = cpu_to_fdt32(
 243                                                 ETH_1G_MDIO_PHY_MASK);
 244                                 prop_val.phy_mode = "rgmii";
 245                                 pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
 246                                                    ETH_2_MDIO);
 247                         }
 248                 break;
 249                 case SERDES_2_5_G_PROTOCOL:
 250                         if (i == 0) {
 251                                 prop_val.busid = cpu_to_fdt32(
 252                                                 ETH_1_2_5G_BUS_ID);
 253                                 prop_val.phyid = cpu_to_fdt32(
 254                                                 ETH_1_2_5G_PHY_ID);
 255                                 prop_val.mux_val = cpu_to_fdt32(
 256                                                 ETH_1_2_5G_MDIO_MUX);
 257                                 prop_val.phy_mask = cpu_to_fdt32(
 258                                                 ETH_2_5G_MDIO_PHY_MASK);
 259                                 prop_val.phy_mode = "sgmii-2500";
 260                                 pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
 261                                                    ETH_1_MDIO);
 262                         } else {
 263                                 prop_val.busid = cpu_to_fdt32(
 264                                                 ETH_2_2_5G_BUS_ID);
 265                                 prop_val.phyid = cpu_to_fdt32(
 266                                                 ETH_2_2_5G_PHY_ID);
 267                                 prop_val.mux_val = cpu_to_fdt32(
 268                                                 ETH_2_2_5G_MDIO_MUX);
 269                                 prop_val.phy_mask = cpu_to_fdt32(
 270                                                 ETH_2_5G_MDIO_PHY_MASK);
 271                                 prop_val.phy_mode = "sgmii-2500";
 272                                 pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
 273                                                    ETH_2_MDIO);
 274                         }
 275                 break;
 276                 default:
 277                         printf("serdes:[%d]\n", srds_s1);
 278                 }
 279         }
 280 }
 281
 282 #ifdef CONFIG_OF_BOARD_SETUP
 283 int ft_board_setup(void *blob, struct bd_info *bd)
 284 {
 285         arch_fixup_fdt(blob);
 286
 287         ft_cpu_setup(blob, bd);
 288         fdt_fsl_fixup_of_pfe(blob);
 289
 290         return 0;
 291 }
 292 #endif