board/freescale/ls1012afrdm/ls1012afrdm.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2017-2018, 2021 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <fdt_support.h>
   8 #include <i2c.h>
   9 #include <asm/cache.h>
  10 #include <init.h>
  11 #include <asm/global_data.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/fsl_serdes.h>
  15 #ifdef CONFIG_FSL_LS_PPA
  16 #include <asm/arch/ppa.h>
  17 #endif
  18 #include <asm/arch/mmu.h>
  19 #include <asm/arch/soc.h>
  20 #include <fsl_esdhc.h>
  21 #include <hwconfig.h>
  22 #include <env_internal.h>
  23 #include <fsl_mmdc.h>
  24 #include <netdev.h>
  25 #include <net/pfe_eth/pfe/pfe_hw.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 static inline int get_board_version(void)
  30 {
  31         uint32_t val;
  32 #ifdef CONFIG_TARGET_LS1012AFRDM
  33         val = 0;
  34 #else
  35         struct ccsr_gpio *pgpio = (void *)(GPIO2_BASE_ADDR);
  36
  37         val = in_be32(&pgpio->gpdat) & BOARD_REV_MASK;/*Get GPIO2 11,12,14*/
  38
  39 #endif
  40         return val;
  41 }
  42
  43 int checkboard(void)
  44 {
  45 #ifdef CONFIG_TARGET_LS1012AFRDM
  46         puts("Board: LS1012AFRDM ");
  47 #else
  48         int rev;
  49
  50         rev = get_board_version();
  51
  52         puts("Board: FRWY-LS1012A ");
  53
  54         puts("Version");
  55
  56         switch (rev) {
  57         case BOARD_REV_A_B:
  58                 puts(": RevA/B ");
  59                 break;
  60         case BOARD_REV_C:
  61                 puts(": RevC ");
  62                 break;
  63         default:
  64                 puts(": unknown");
  65                 break;
  66         }
  67 #endif
  68
  69         return 0;
  70 }
  71
  72 #ifdef CONFIG_TARGET_LS1012AFRWY
  73 int esdhc_status_fixup(void *blob, const char *compat)
  74 {
  75         char esdhc0_path[] = "/soc/esdhc@1560000";
  76         char esdhc1_path[] = "/soc/esdhc@1580000";
  77
  78         do_fixup_by_path(blob, esdhc0_path, "status", "okay",
  79                          sizeof("okay"), 1);
  80
  81         do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
  82                          sizeof("disabled"), 1);
  83         return 0;
  84 }
  85 #endif
  86
  87 #ifdef CONFIG_TFABOOT
  88 int dram_init(void)
  89 {
  90 #ifdef CONFIG_TARGET_LS1012AFRWY
  91         int board_rev;
  92 #endif
  93
  94         gd->ram_size = tfa_get_dram_size();
  95
  96         if (!gd->ram_size) {
  97 #ifdef CONFIG_TARGET_LS1012AFRWY
  98                 board_rev = get_board_version();
  99
 100                 if (board_rev & BOARD_REV_C)
 101                         gd->ram_size = SYS_SDRAM_SIZE_1024;
 102                 else
 103                         gd->ram_size = SYS_SDRAM_SIZE_512;
 104 #else
 105                 gd->ram_size = CFG_SYS_SDRAM_SIZE;
 106 #endif
 107         }
 108         return 0;
 109 }
 110 #else
 111 int dram_init(void)
 112 {
 113 #ifdef CONFIG_TARGET_LS1012AFRWY
 114         int board_rev;
 115 #endif
 116         struct fsl_mmdc_info mparam = {
 117                 0x04180000,     /* mdctl */
 118                 0x00030035,     /* mdpdc */
 119                 0x12554000,     /* mdotc */
 120                 0xbabf7954,     /* mdcfg0 */
 121                 0xdb328f64,     /* mdcfg1 */
 122                 0x01ff00db,     /* mdcfg2 */
 123                 0x00001680,     /* mdmisc */
 124                 0x0f3c8000,     /* mdref */
 125                 0x00002000,     /* mdrwd */
 126                 0x00bf1023,     /* mdor */
 127                 0x0000003f,     /* mdasp */
 128                 0x0000022a,     /* mpodtctrl */
 129                 0xa1390003,     /* mpzqhwctrl */
 130         };
 131
 132 #ifdef CONFIG_TARGET_LS1012AFRWY
 133         board_rev = get_board_version();
 134
 135         if (board_rev == BOARD_REV_C) {
 136                 mparam.mdctl = 0x05180000;
 137                 gd->ram_size = SYS_SDRAM_SIZE_1024;
 138         } else {
 139                 gd->ram_size = SYS_SDRAM_SIZE_512;
 140         }
 141 #else
 142         gd->ram_size = CFG_SYS_SDRAM_SIZE;
 143 #endif
 144         mmdc_init(&mparam);
 145
 146 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
 147         /* This will break-before-make MMU for DDR */
 148         update_early_mmu_table();
 149 #endif
 150
 151         return 0;
 152 }
 153 #endif
 154
 155 int board_early_init_f(void)
 156 {
 157         fsl_lsch2_early_init_f();
 158
 159         return 0;
 160 }
 161
 162 int board_init(void)
 163 {
 164         struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
 165                                         CONFIG_SYS_CCI400_OFFSET);
 166
 167         /*
 168          * Set CCI-400 control override register to enable barrier
 169          * transaction
 170          */
 171         if (current_el() == 3)
 172                 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
 173
 174 #ifdef CONFIG_FSL_LS_PPA
 175         ppa_init();
 176 #endif
 177         return 0;
 178 }
 179
 180 #ifdef CONFIG_FSL_PFE
 181 void board_quiesce_devices(void)
 182 {
 183         pfe_command_stop(0, NULL);
 184 }
 185 #endif
 186
 187 int ft_board_setup(void *blob, struct bd_info *bd)
 188 {
 189         arch_fixup_fdt(blob);
 190
 191         ft_cpu_setup(blob, bd);
 192
 193         return 0;
 194 }