1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2017-2018 NXP
7 #include <fdt_support.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/fsl_serdes.h>
12 #ifdef CONFIG_FSL_LS_PPA
13 #include <asm/arch/ppa.h>
15 #include <asm/arch/mmu.h>
16 #include <asm/arch/soc.h>
17 #include <fsl_esdhc.h>
19 #include <env_internal.h>
24 DECLARE_GLOBAL_DATA_PTR;
26 static inline int get_board_version(void)
29 #ifdef CONFIG_TARGET_LS1012AFRDM
32 struct ccsr_gpio *pgpio = (void *)(GPIO2_BASE_ADDR);
34 val = in_be32(&pgpio->gpdat) & BOARD_REV_MASK;/*Get GPIO2 11,12,14*/
42 #ifdef CONFIG_TARGET_LS1012AFRDM
43 puts("Board: LS1012AFRDM ");
47 rev = get_board_version();
49 puts("Board: FRWY-LS1012A ");
69 #ifdef CONFIG_TARGET_LS1012AFRWY
70 int esdhc_status_fixup(void *blob, const char *compat)
72 char esdhc0_path[] = "/soc/esdhc@1560000";
73 char esdhc1_path[] = "/soc/esdhc@1580000";
75 do_fixup_by_path(blob, esdhc0_path, "status", "okay",
78 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
79 sizeof("disabled"), 1);
87 #ifdef CONFIG_TARGET_LS1012AFRWY
91 gd->ram_size = tfa_get_dram_size();
94 #ifdef CONFIG_TARGET_LS1012AFRWY
95 board_rev = get_board_version();
97 if (board_rev & BOARD_REV_C)
98 gd->ram_size = SYS_SDRAM_SIZE_1024;
100 gd->ram_size = SYS_SDRAM_SIZE_512;
102 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
110 #ifdef CONFIG_TARGET_LS1012AFRWY
113 struct fsl_mmdc_info mparam = {
114 0x04180000, /* mdctl */
115 0x00030035, /* mdpdc */
116 0x12554000, /* mdotc */
117 0xbabf7954, /* mdcfg0 */
118 0xdb328f64, /* mdcfg1 */
119 0x01ff00db, /* mdcfg2 */
120 0x00001680, /* mdmisc */
121 0x0f3c8000, /* mdref */
122 0x00002000, /* mdrwd */
123 0x00bf1023, /* mdor */
124 0x0000003f, /* mdasp */
125 0x0000022a, /* mpodtctrl */
126 0xa1390003, /* mpzqhwctrl */
129 #ifdef CONFIG_TARGET_LS1012AFRWY
130 board_rev = get_board_version();
132 if (board_rev == BOARD_REV_C) {
133 mparam.mdctl = 0x05180000;
134 gd->ram_size = SYS_SDRAM_SIZE_1024;
136 gd->ram_size = SYS_SDRAM_SIZE_512;
139 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
143 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
144 /* This will break-before-make MMU for DDR */
145 update_early_mmu_table();
152 int board_early_init_f(void)
154 fsl_lsch2_early_init_f();
161 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
162 CONFIG_SYS_CCI400_OFFSET);
165 * Set CCI-400 control override register to enable barrier
168 if (current_el() == 3)
169 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
171 #ifdef CONFIG_ENV_IS_NOWHERE
172 gd->env_addr = (ulong)&default_environment[0];
175 #ifdef CONFIG_FSL_CAAM
179 #ifdef CONFIG_FSL_LS_PPA
185 int ft_board_setup(void *blob, bd_t *bd)
187 arch_fixup_fdt(blob);
189 ft_cpu_setup(blob, bd);