board/freescale/ls1012afrdm/ls1012afrdm.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2017-2018 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <fdt_support.h>
   8 #include <i2c.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/fsl_serdes.h>
  12 #ifdef CONFIG_FSL_LS_PPA
  13 #include <asm/arch/ppa.h>
  14 #endif
  15 #include <asm/arch/mmu.h>
  16 #include <asm/arch/soc.h>
  17 #include <fsl_esdhc.h>
  18 #include <hwconfig.h>
  19 #include <env_internal.h>
  20 #include <fsl_mmdc.h>
  21 #include <netdev.h>
  22 #include <fsl_sec.h>
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 static inline int get_board_version(void)
  27 {
  28         uint32_t val;
  29 #ifdef CONFIG_TARGET_LS1012AFRDM
  30         val = 0;
  31 #else
  32         struct ccsr_gpio *pgpio = (void *)(GPIO2_BASE_ADDR);
  33
  34         val = in_be32(&pgpio->gpdat) & BOARD_REV_MASK;/*Get GPIO2 11,12,14*/
  35
  36 #endif
  37         return val;
  38 }
  39
  40 int checkboard(void)
  41 {
  42 #ifdef CONFIG_TARGET_LS1012AFRDM
  43         puts("Board: LS1012AFRDM ");
  44 #else
  45         int rev;
  46
  47         rev = get_board_version();
  48
  49         puts("Board: FRWY-LS1012A ");
  50
  51         puts("Version");
  52
  53         switch (rev) {
  54         case BOARD_REV_A_B:
  55                 puts(": RevA/B ");
  56                 break;
  57         case BOARD_REV_C:
  58                 puts(": RevC ");
  59                 break;
  60         default:
  61                 puts(": unknown");
  62                 break;
  63         }
  64 #endif
  65
  66         return 0;
  67 }
  68
  69 #ifdef CONFIG_TARGET_LS1012AFRWY
  70 int esdhc_status_fixup(void *blob, const char *compat)
  71 {
  72         char esdhc0_path[] = "/soc/esdhc@1560000";
  73         char esdhc1_path[] = "/soc/esdhc@1580000";
  74
  75         do_fixup_by_path(blob, esdhc0_path, "status", "okay",
  76                          sizeof("okay"), 1);
  77
  78         do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
  79                          sizeof("disabled"), 1);
  80         return 0;
  81 }
  82 #endif
  83
  84 #ifdef CONFIG_TFABOOT
  85 int dram_init(void)
  86 {
  87 #ifdef CONFIG_TARGET_LS1012AFRWY
  88         int board_rev;
  89 #endif
  90
  91         gd->ram_size = tfa_get_dram_size();
  92
  93         if (!gd->ram_size) {
  94 #ifdef CONFIG_TARGET_LS1012AFRWY
  95                 board_rev = get_board_version();
  96
  97                 if (board_rev & BOARD_REV_C)
  98                         gd->ram_size = SYS_SDRAM_SIZE_1024;
  99                 else
 100                         gd->ram_size = SYS_SDRAM_SIZE_512;
 101 #else
 102                 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 103 #endif
 104         }
 105         return 0;
 106 }
 107 #else
 108 int dram_init(void)
 109 {
 110 #ifdef CONFIG_TARGET_LS1012AFRWY
 111         int board_rev;
 112 #endif
 113         struct fsl_mmdc_info mparam = {
 114                 0x04180000,     /* mdctl */
 115                 0x00030035,     /* mdpdc */
 116                 0x12554000,     /* mdotc */
 117                 0xbabf7954,     /* mdcfg0 */
 118                 0xdb328f64,     /* mdcfg1 */
 119                 0x01ff00db,     /* mdcfg2 */
 120                 0x00001680,     /* mdmisc */
 121                 0x0f3c8000,     /* mdref */
 122                 0x00002000,     /* mdrwd */
 123                 0x00bf1023,     /* mdor */
 124                 0x0000003f,     /* mdasp */
 125                 0x0000022a,     /* mpodtctrl */
 126                 0xa1390003,     /* mpzqhwctrl */
 127         };
 128
 129 #ifdef CONFIG_TARGET_LS1012AFRWY
 130         board_rev = get_board_version();
 131
 132         if (board_rev == BOARD_REV_C) {
 133                 mparam.mdctl = 0x05180000;
 134                 gd->ram_size = SYS_SDRAM_SIZE_1024;
 135         } else {
 136                 gd->ram_size = SYS_SDRAM_SIZE_512;
 137         }
 138 #else
 139         gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 140 #endif
 141         mmdc_init(&mparam);
 142
 143 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
 144         /* This will break-before-make MMU for DDR */
 145         update_early_mmu_table();
 146 #endif
 147
 148         return 0;
 149 }
 150 #endif
 151
 152 int board_early_init_f(void)
 153 {
 154         fsl_lsch2_early_init_f();
 155
 156         return 0;
 157 }
 158
 159 int board_init(void)
 160 {
 161         struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
 162                                         CONFIG_SYS_CCI400_OFFSET);
 163
 164         /*
 165          * Set CCI-400 control override register to enable barrier
 166          * transaction
 167          */
 168         if (current_el() == 3)
 169                 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
 170
 171 #ifdef CONFIG_ENV_IS_NOWHERE
 172         gd->env_addr = (ulong)&default_environment[0];
 173 #endif
 174
 175 #ifdef CONFIG_FSL_CAAM
 176         sec_init();
 177 #endif
 178
 179 #ifdef CONFIG_FSL_LS_PPA
 180         ppa_init();
 181 #endif
 182         return 0;
 183 }
 184
 185 int ft_board_setup(void *blob, bd_t *bd)
 186 {
 187         arch_fixup_fdt(blob);
 188
 189         ft_cpu_setup(blob, bd);
 190
 191         return 0;
 192 }