1 // SPDX-License-Identifier: GPL-2.0+
14 #include <asm/mach-imx/iomux-v3.h>
15 #include <asm-generic/gpio.h>
16 #include <fsl_esdhc_imx.h>
18 #include <asm/arch/imx8mq_pins.h>
19 #include <asm/arch/sys_proto.h>
20 #include <asm/mach-imx/gpio.h>
21 #include <asm/mach-imx/mxc_i2c.h>
22 #include <asm/arch/clock.h>
24 #include <linux/bitops.h>
25 #include <power/pmic.h>
26 #include <power/pfuze100_pmic.h>
27 #include "../common/pfuze.h"
29 DECLARE_GLOBAL_DATA_PTR;
31 #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
33 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
35 static iomux_v3_cfg_t const wdog_pads[] = {
36 IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
39 static iomux_v3_cfg_t const uart_pads[] = {
40 IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
41 IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
44 int board_early_init_f(void)
46 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
48 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
51 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
57 static int setup_fec(void)
59 struct iomuxc_gpr_base_regs *gpr =
60 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
62 /* Use 125M anatop REF_CLK1 for ENET1, not from external */
63 clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
64 return set_clk_enet(ENET_125MHZ);
67 int board_phy_config(struct phy_device *phydev)
69 /* enable rgmii rxc skew and phy mode select to RGMII copper */
70 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
71 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
73 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
74 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
76 if (phydev->drv->config)
77 phydev->drv->config(phydev);
91 int board_mmc_get_env_dev(int devno)
96 int board_late_init(void)
98 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
99 env_set("board_name", "EVK");
100 env_set("board_rev", "iMX8MQ");