1 // SPDX-License-Identifier: GPL-2.0+
6 #include <linux/kernel.h>
7 #include <asm/arch/ddr.h>
9 struct dram_cfg_param ddr_ddrc_cfg[] = {
10 /** Initialize DDRC registers **/
13 { 0x3d400000, 0xa3080020 },
14 { 0x3d400020, 0x323 },
15 { 0x3d400024, 0x1e84800 },
16 { 0x3d400064, 0x7a0118 },
17 { 0x3d4000d0, 0xc00307a3 },
18 { 0x3d4000d4, 0xc50000 },
19 { 0x3d4000dc, 0xf4003f },
20 { 0x3d4000e0, 0x330000 },
21 { 0x3d4000e8, 0x460048 },
22 { 0x3d4000ec, 0x150048 },
23 { 0x3d400100, 0x2028222a },
24 { 0x3d400104, 0x807bf },
25 { 0x3d40010c, 0xe0e000 },
26 { 0x3d400110, 0x12040a12 },
27 { 0x3d400114, 0x2050f0f },
28 { 0x3d400118, 0x1010009 },
29 { 0x3d40011c, 0x501 },
30 { 0x3d400130, 0x20800 },
31 { 0x3d400134, 0xe100002 },
32 { 0x3d400138, 0x120 },
33 { 0x3d400144, 0xc80064 },
34 { 0x3d400180, 0x3e8001e },
35 { 0x3d400184, 0x3207a12 },
37 { 0x3d400190, 0x49f820e },
38 { 0x3d400194, 0x80303 },
39 { 0x3d4001b4, 0x1f0e },
40 { 0x3d4001a0, 0xe0400018 },
41 { 0x3d4001a4, 0xdf00e4 },
42 { 0x3d4001a8, 0x80000000 },
46 { 0x3d4000f4, 0xc99 },
47 { 0x3d400108, 0x9121c1c },
50 { 0x3d400210, 0x1f1f },
51 { 0x3d400204, 0x80808 },
52 { 0x3d400214, 0x7070707 },
53 { 0x3d400218, 0x68070707 },
54 { 0x3d40021c, 0xf08 },
55 { 0x3d400250, 0x29001701 },
57 { 0x3d40025c, 0x4000030 },
58 { 0x3d400264, 0x900093e7 },
59 { 0x3d40026c, 0x2005574 },
60 { 0x3d400400, 0x111 },
61 { 0x3d400408, 0x72ff },
62 { 0x3d400494, 0x2100e07 },
63 { 0x3d400498, 0x620096 },
64 { 0x3d40049c, 0x1100e07 },
65 { 0x3d4004a0, 0xc8012c },
67 { 0x3d402024, 0x7d00 },
68 { 0x3d402050, 0x20d040 },
69 { 0x3d402064, 0xc001c },
70 { 0x3d4020dc, 0x840000 },
71 { 0x3d4020e0, 0x310000 },
72 { 0x3d4020e8, 0x66004d },
73 { 0x3d4020ec, 0x16004d },
74 { 0x3d402100, 0xa040305 },
75 { 0x3d402104, 0x30407 },
76 { 0x3d402108, 0x203060b },
77 { 0x3d40210c, 0x505000 },
78 { 0x3d402110, 0x2040202 },
79 { 0x3d402114, 0x2030202 },
80 { 0x3d402118, 0x1010004 },
81 { 0x3d40211c, 0x301 },
82 { 0x3d402130, 0x20300 },
83 { 0x3d402134, 0xa100002 },
85 { 0x3d402144, 0x14000a },
86 { 0x3d402180, 0x640004 },
87 { 0x3d402190, 0x3818200 },
88 { 0x3d402194, 0x80303 },
89 { 0x3d4021b4, 0x100 },
90 { 0x3d4020f4, 0xc99 },
92 { 0x3d403024, 0x30d400 },
93 { 0x3d403050, 0x20d040 },
94 { 0x3d403064, 0x30007 },
95 { 0x3d4030dc, 0x840000 },
96 { 0x3d4030e0, 0x310000 },
97 { 0x3d4030e8, 0x66004d },
98 { 0x3d4030ec, 0x16004d },
99 { 0x3d403100, 0xa010102 },
100 { 0x3d403104, 0x30404 },
101 { 0x3d403108, 0x203060b },
102 { 0x3d40310c, 0x505000 },
103 { 0x3d403110, 0x2040202 },
104 { 0x3d403114, 0x2030202 },
105 { 0x3d403118, 0x1010004 },
106 { 0x3d40311c, 0x301 },
107 { 0x3d403130, 0x20300 },
108 { 0x3d403134, 0xa100002 },
110 { 0x3d403144, 0x50003 },
111 { 0x3d403180, 0x190004 },
112 { 0x3d403190, 0x3818200 },
113 { 0x3d403194, 0x80303 },
114 { 0x3d4031b4, 0x100 },
118 /* PHY Initialize Configuration */
119 struct dram_cfg_param ddr_ddrphy_cfg[] = {
327 /* ddr phy trained csr */
328 struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
1050 /* P0 message block paremeter for training firmware */
1051 struct dram_cfg_param ddr_fsp0_cfg[] = {
1055 { 0x54005, 0x2228 },
1057 { 0x54008, 0x131f },
1062 { 0x54019, 0x3ff4 },
1064 { 0x5401b, 0x4866 },
1065 { 0x5401c, 0x4800 },
1067 { 0x5401f, 0x3ff4 },
1069 { 0x54021, 0x4866 },
1070 { 0x54022, 0x4800 },
1072 { 0x5402b, 0x1000 },
1074 { 0x54032, 0xf400 },
1075 { 0x54033, 0x333f },
1076 { 0x54034, 0x6600 },
1079 { 0x54037, 0x1600 },
1080 { 0x54038, 0xf400 },
1081 { 0x54039, 0x333f },
1082 { 0x5403a, 0x6600 },
1085 { 0x5403d, 0x1600 },
1089 /* P1 message block paremeter for training firmware */
1090 struct dram_cfg_param ddr_fsp1_cfg[] = {
1095 { 0x54005, 0x2228 },
1097 { 0x54008, 0x121f },
1104 { 0x5401b, 0x4846 },
1105 { 0x5401c, 0x4800 },
1109 { 0x54021, 0x4846 },
1110 { 0x54022, 0x4800 },
1112 { 0x5402b, 0x1000 },
1114 { 0x54032, 0x8400 },
1115 { 0x54033, 0x3300 },
1116 { 0x54034, 0x4600 },
1119 { 0x54037, 0x1500 },
1120 { 0x54038, 0x8400 },
1121 { 0x54039, 0x3300 },
1122 { 0x5403a, 0x4600 },
1125 { 0x5403d, 0x1500 },
1129 /* P2 message block paremeter for training firmware */
1130 struct dram_cfg_param ddr_fsp2_cfg[] = {
1135 { 0x54005, 0x2228 },
1137 { 0x54008, 0x121f },
1144 { 0x5401b, 0x4846 },
1145 { 0x5401c, 0x4800 },
1149 { 0x54021, 0x4846 },
1150 { 0x54022, 0x4800 },
1152 { 0x5402b, 0x1000 },
1154 { 0x54032, 0x8400 },
1155 { 0x54033, 0x3300 },
1156 { 0x54034, 0x4600 },
1159 { 0x54037, 0x1500 },
1160 { 0x54038, 0x8400 },
1161 { 0x54039, 0x3300 },
1162 { 0x5403a, 0x4600 },
1165 { 0x5403d, 0x1500 },
1169 /* P0 2D message block paremeter for training firmware */
1170 struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
1174 { 0x54005, 0x2228 },
1181 { 0x54010, 0x1f7f },
1183 { 0x54019, 0x3ff4 },
1185 { 0x5401b, 0x4866 },
1186 { 0x5401c, 0x4800 },
1188 { 0x5401f, 0x3ff4 },
1190 { 0x54021, 0x4866 },
1191 { 0x54022, 0x4800 },
1193 { 0x5402b, 0x1000 },
1195 { 0x54032, 0xf400 },
1196 { 0x54033, 0x333f },
1197 { 0x54034, 0x6600 },
1200 { 0x54037, 0x1600 },
1201 { 0x54038, 0xf400 },
1202 { 0x54039, 0x333f },
1203 { 0x5403a, 0x6600 },
1206 { 0x5403d, 0x1600 },
1210 /* DRAM PHY init engine image */
1211 struct dram_cfg_param ddr_phy_pie[] = {
1270 { 0x9005c, 0x40c0 },
1276 { 0x90062, 0x4040 },
1346 { 0x40001, 0x4008 },
1350 { 0x40002, 0x4040 },
1360 { 0x40044, 0x1740 },
1368 { 0x40046, 0x2001 },
1372 { 0x40047, 0x2800 },
1380 { 0x40049, 0x1400 },
1390 { 0x4000c, 0x4028 },
1402 { 0x4000f, 0x4040 },
1406 { 0x40010, 0x2604 },
1413 { 0x40071, 0x2002 },
1418 { 0x40013, 0x2604 },
1425 { 0x40074, 0x2002 },
1426 { 0x40015, 0x4040 },
1432 { 0x40056, 0x1200 },
1436 { 0x40057, 0x1300 },
1440 { 0x40058, 0x1200 },
1444 { 0x40059, 0x1300 },
1446 { 0x4001a, 0x4808 },
1487 { 0x900c9, 0x8568 },
1496 { 0x900d2, 0x8558 },
1501 { 0x900d7, 0x1ff8 },
1502 { 0x900d8, 0x85a8 },
1511 { 0x900e1, 0x8310 },
1514 { 0x900e4, 0xa310 },
1526 { 0x900f0, 0x8310 },
1529 { 0x900f3, 0xa310 },
1531 { 0x900f5, 0x1ff8 },
1532 { 0x900f6, 0x85a8 },
1544 { 0x90102, 0x8b10 },
1547 { 0x90105, 0xab10 },
1559 { 0x90111, 0x8b10 },
1562 { 0x90114, 0xab10 },
1577 { 0x90123, 0x8080 },
1592 { 0x90132, 0x8080 },
1598 { 0x90138, 0x8568 },
1607 { 0x90141, 0x8558 },
1619 { 0x9014d, 0x8558 },
1637 { 0x9015f, 0x8140 },
1640 { 0x90162, 0x8138 },
1667 { 0x9017d, 0x8140 },
1715 { 0x9000f, 0x6110 },
1716 { 0x90010, 0x2152 },
1717 { 0x90011, 0xdfbd },
1718 { 0x90012, 0x2060 },
1719 { 0x90013, 0x6152 },
1745 { 0x10002, 0x6209 },
1759 { 0x11002, 0x6209 },
1773 { 0x12002, 0x6209 },
1787 { 0x13002, 0x6209 },
1803 struct dram_fsp_msg ddr_dram_fsp_msg[] = {
1807 .fw_type = FW_1D_IMAGE,
1808 .fsp_cfg = ddr_fsp0_cfg,
1809 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
1814 .fw_type = FW_1D_IMAGE,
1815 .fsp_cfg = ddr_fsp1_cfg,
1816 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
1821 .fw_type = FW_1D_IMAGE,
1822 .fsp_cfg = ddr_fsp2_cfg,
1823 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
1828 .fw_type = FW_2D_IMAGE,
1829 .fsp_cfg = ddr_fsp0_2d_cfg,
1830 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
1834 /* ddr timing config params */
1835 struct dram_timing_info dram_timing = {
1836 .ddrc_cfg = ddr_ddrc_cfg,
1837 .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
1838 .ddrphy_cfg = ddr_ddrphy_cfg,
1839 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
1840 .fsp_msg = ddr_dram_fsp_msg,
1841 .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
1842 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
1843 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
1844 .ddrphy_pie = ddr_phy_pie,
1845 .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
1846 .fsp_table = { 4000, 400, 100, },