2 * Copyright 2018-2019 NXP
4 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/mach-imx/iomux-v3.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/imx8mn_pins.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/mach-imx/boot_mode.h>
17 #include <asm/arch/ddr.h>
19 #include <dm/uclass.h>
20 #include <dm/device.h>
21 #include <dm/uclass-internal.h>
22 #include <dm/device-internal.h>
24 DECLARE_GLOBAL_DATA_PTR;
26 int spl_board_boot_device(enum boot_device boot_dev_spl)
28 return BOOT_DEVICE_BOOTROM;
31 void spl_dram_init(void)
33 ddr_init(&dram_timing);
36 void spl_board_init(void)
41 puts("Normal Boot\n");
43 ret = uclass_get_device_by_name(UCLASS_CLK,
44 "clock-controller@30380000",
47 printf("Failed to find clock node. Check device tree\n");
50 #ifdef CONFIG_SPL_LOAD_FIT
51 int board_fit_config_name_match(const char *name)
53 /* Just empty function now - can't decide what to choose */
54 debug("%s: %s\n", __func__, name);
60 #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
61 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
63 static iomux_v3_cfg_t const uart_pads[] = {
64 IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
65 IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
68 static iomux_v3_cfg_t const wdog_pads[] = {
69 IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
72 int board_early_init_f(void)
74 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
76 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
80 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
87 void board_init_f(ulong dummy)
99 preloader_console_init();
102 memset(__bss_start, 0, __bss_end - __bss_start);
106 debug("spl_init() failed: %d\n", ret);
112 /* DDR initialization */
115 board_init_r(NULL, 0);