4 * SPDX-License-Identifier: GPL-2.0+
6 * Generated code from MX8M_DDR_tool
7 * Align with uboot version:
8 * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga
11 #include <linux/kernel.h>
12 #include <asm/arch/ddr.h>
14 struct dram_cfg_param ddr_ddrc_cfg[] = {
15 /** Initialize DDRC registers **/
16 { 0x3d400000, 0x81040010 },
18 { 0x3d400034, 0x221306 },
19 { 0x3d400050, 0x210070 },
20 { 0x3d400054, 0x10008 },
22 { 0x3d400064, 0x6100dc },
24 { 0x3d4000c4, 0x1000 },
25 { 0x3d4000d0, 0xc00200c5 },
26 { 0x3d4000d4, 0x500000 },
27 { 0x3d4000dc, 0x2340105 },
29 { 0x3d4000e4, 0x110000 },
30 { 0x3d4000e8, 0x2000600 },
31 { 0x3d4000ec, 0x410 },
33 { 0x3d4000f4, 0xec7 },
34 { 0x3d400100, 0xd0c1b0d },
35 { 0x3d400104, 0x30313 },
36 { 0x3d400108, 0x508060a },
37 { 0x3d40010c, 0x400c },
38 { 0x3d400110, 0x6030306 },
39 { 0x3d400114, 0x4040302 },
40 { 0x3d40011c, 0x404 },
41 { 0x3d400120, 0x5050d08 },
42 { 0x3d400124, 0x20308 },
43 { 0x3d40012c, 0x1406010e },
46 { 0x3d400180, 0x1000040 },
47 { 0x3d400184, 0x30d4 },
48 { 0x3d400190, 0x38b8204 },
49 { 0x3d400194, 0x2020303 },
50 { 0x3d400198, 0x7f04011 },
52 { 0x3d4001a0, 0xe0400018 },
53 { 0x3d4001a4, 0x48005a },
54 { 0x3d4001a8, 0x80000000 },
56 { 0x3d4001b4, 0xb04 },
60 { 0x3d400200, 0x3f1f },
61 { 0x3d400204, 0x3f0909 },
62 { 0x3d400208, 0x700 },
64 { 0x3d400210, 0x1f1f },
65 { 0x3d400214, 0x7070707 },
66 { 0x3d400218, 0x7070707 },
67 { 0x3d40021c, 0xf07 },
68 { 0x3d400220, 0x3f01 },
69 { 0x3d400240, 0x600061c },
70 { 0x3d400244, 0x1323 },
71 { 0x3d400400, 0x100 },
72 { 0x3d400250, 0x317d1a07 },
74 { 0x3d40025c, 0x2a001b76 },
75 { 0x3d400264, 0x7300b473 },
76 { 0x3d40026c, 0x30000e06 },
79 { 0x3d400404, 0x13193 },
80 { 0x3d400408, 0x6096 },
82 { 0x3d400494, 0x2000c00 },
83 { 0x3d400498, 0x3c00db },
84 { 0x3d40049c, 0x100009 },
86 { 0x3d402050, 0x210070 },
87 { 0x3d402064, 0x400093 },
88 { 0x3d4020dc, 0x40105 },
90 { 0x3d4020e8, 0x2000600 },
92 { 0x3d402100, 0xb081209 },
93 { 0x3d402104, 0x2020d },
94 { 0x3d402108, 0x5050309 },
95 { 0x3d40210c, 0x400c },
96 { 0x3d402110, 0x5030206 },
97 { 0x3d402114, 0x3030202 },
98 { 0x3d40211c, 0x303 },
99 { 0x3d402120, 0x4040d06 },
100 { 0x3d402124, 0x20208 },
101 { 0x3d40212c, 0x1205010e },
104 { 0x3d402180, 0x1000040 },
105 { 0x3d402190, 0x3858204 },
106 { 0x3d402194, 0x2020303 },
107 { 0x3d4021b4, 0x504 },
109 { 0x3d402240, 0x6000604 },
110 { 0x3d4020f4, 0xec7 },
113 /* PHY Initialize Configuration */
114 struct dram_cfg_param ddr_ddrphy_cfg[] = {
217 /* ddr phy trained csr */
218 struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
744 /* P0 message block paremeter for training firmware */
745 struct dram_cfg_param ddr_fsp0_cfg[] = {
769 /* P1 message block paremeter for training firmware */
770 struct dram_cfg_param ddr_fsp1_cfg[] = {
795 /* P0 2D message block paremeter for training firmware */
796 struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
820 /* DRAM PHY init engine image */
821 struct dram_cfg_param ddr_phy_pie[] = {
1003 { 0x12000d, 0x29a },
1008 { 0x9000f, 0x6110 },
1009 { 0x90010, 0x2152 },
1010 { 0x90011, 0xdfbd },
1011 { 0x90012, 0xffff },
1012 { 0x90013, 0x6152 },
1019 struct dram_fsp_msg ddr_dram_fsp_msg[] = {
1023 .fw_type = FW_1D_IMAGE,
1024 .fsp_cfg = ddr_fsp0_cfg,
1025 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
1030 .fw_type = FW_1D_IMAGE,
1031 .fsp_cfg = ddr_fsp1_cfg,
1032 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
1037 .fw_type = FW_2D_IMAGE,
1038 .fsp_cfg = ddr_fsp0_2d_cfg,
1039 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
1043 /* ddr timing config params */
1044 struct dram_timing_info dram_timing = {
1045 .ddrc_cfg = ddr_ddrc_cfg,
1046 .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
1047 .ddrphy_cfg = ddr_ddrphy_cfg,
1048 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
1049 .fsp_msg = ddr_dram_fsp_msg,
1050 .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
1051 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
1052 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
1053 .ddrphy_pie = ddr_phy_pie,
1054 .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
1055 .fsp_table = { 1600, 1066, },