board/freescale/imx8mm_evk/spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <cpu_func.h>
   8 #include <hang.h>
   9 #include <image.h>
  10 #include <init.h>
  11 #include <spl.h>
  12 #include <asm/io.h>
  13 #include <asm/mach-imx/iomux-v3.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/imx8mm_pins.h>
  16 #include <asm/arch/sys_proto.h>
  17 #include <asm/mach-imx/boot_mode.h>
  18 #include <asm/arch/ddr.h>
  19
  20 #include <dm/uclass.h>
  21 #include <dm/device.h>
  22 #include <dm/uclass-internal.h>
  23 #include <dm/device-internal.h>
  24
  25 #include <power/pmic.h>
  26 #include <power/bd71837.h>
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 int spl_board_boot_device(enum boot_device boot_dev_spl)
  31 {
  32         switch (boot_dev_spl) {
  33         case SD2_BOOT:
  34         case MMC2_BOOT:
  35                 return BOOT_DEVICE_MMC1;
  36         case SD3_BOOT:
  37         case MMC3_BOOT:
  38                 return BOOT_DEVICE_MMC2;
  39         default:
  40                 return BOOT_DEVICE_NONE;
  41         }
  42 }
  43
  44 static void spl_dram_init(void)
  45 {
  46         ddr_init(&dram_timing);
  47 }
  48
  49 void spl_board_init(void)
  50 {
  51         puts("Normal Boot\n");
  52 }
  53
  54 #ifdef CONFIG_SPL_LOAD_FIT
  55 int board_fit_config_name_match(const char *name)
  56 {
  57         /* Just empty function now - can't decide what to choose */
  58         debug("%s: %s\n", __func__, name);
  59
  60         return 0;
  61 }
  62 #endif
  63
  64 #define UART_PAD_CTRL   (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
  65 #define WDOG_PAD_CTRL   (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
  66
  67 static iomux_v3_cfg_t const uart_pads[] = {
  68         IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  69         IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  70 };
  71
  72 static iomux_v3_cfg_t const wdog_pads[] = {
  73         IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
  74 };
  75
  76 int board_early_init_f(void)
  77 {
  78         struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
  79
  80         imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
  81
  82         set_wdog_reset(wdog);
  83
  84         imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  85
  86         return 0;
  87 }
  88
  89 static int power_init_board(void)
  90 {
  91         struct udevice *dev;
  92         int ret;
  93
  94         ret = pmic_get("pmic@4b", &dev);
  95         if (ret == -ENODEV) {
  96                 puts("No pmic\n");
  97                 return 0;
  98         }
  99         if (ret != 0)
 100                 return ret;
 101
 102         /* decrease RESET key long push time from the default 10s to 10ms */
 103         pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0);
 104
 105         /* unlock the PMIC regs */
 106         pmic_reg_write(dev, BD718XX_REGLOCK, 0x1);
 107
 108         /* increase VDD_SOC to typical value 0.85v before first DRAM access */
 109         pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);
 110
 111         /* increase VDD_DRAM to 0.975v for 3Ghz DDR */
 112         pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
 113
 114 #ifndef CONFIG_IMX8M_LPDDR4
 115         /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
 116         pmic_reg_write(dev, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28);
 117 #endif
 118
 119         /* lock the PMIC regs */
 120         pmic_reg_write(dev, BD718XX_REGLOCK, 0x11);
 121
 122         return 0;
 123 }
 124
 125 void board_init_f(ulong dummy)
 126 {
 127         struct udevice *dev;
 128         int ret;
 129
 130         arch_cpu_init();
 131
 132         init_uart_clk(1);
 133
 134         board_early_init_f();
 135
 136         timer_init();
 137
 138         preloader_console_init();
 139
 140         /* Clear the BSS. */
 141         memset(__bss_start, 0, __bss_end - __bss_start);
 142
 143         ret = spl_early_init();
 144         if (ret) {
 145                 debug("spl_early_init() failed: %d\n", ret);
 146                 hang();
 147         }
 148
 149         ret = uclass_get_device_by_name(UCLASS_CLK,
 150                                         "clock-controller@30380000",
 151                                         &dev);
 152         if (ret < 0) {
 153                 printf("Failed to find clock node. Check device tree\n");
 154                 hang();
 155         }
 156
 157         enable_tzc380();
 158
 159         power_init_board();
 160
 161         /* DDR initialization */
 162         spl_dram_init();
 163
 164         board_init_r(NULL, 0);
 165 }