2 * Copyright 2009-2010 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
10 #include <asm/fsl_ddr_sdram.h>
12 #define DATARATE_800MHZ 800000000
13 #define DATARATE_900MHZ 900000000
14 #define DATARATE_1000MHZ 1000000000
15 #define DATARATE_1200MHZ 1200000000
16 #define DATARATE_1300MHZ 1300000000
18 #define CONFIG_SYS_DDR_TIMING_3_1200 0x01030000
19 #define CONFIG_SYS_DDR_TIMING_0_1200 0xCC550104
20 #define CONFIG_SYS_DDR_TIMING_1_1200 0x868FAA45
21 #define CONFIG_SYS_DDR_TIMING_2_1200 0x0FB8A912
22 #define CONFIG_SYS_DDR_MODE_1_1200 0x00441A40
23 #define CONFIG_SYS_DDR_MODE_2_1200 0x00100000
24 #define CONFIG_SYS_DDR_INTERVAL_1200 0x12480100
25 #define CONFIG_SYS_DDR_CLK_CTRL_1200 0x02800000
27 #define CONFIG_SYS_DDR_TIMING_3_1000 0x00020000
28 #define CONFIG_SYS_DDR_TIMING_0_1000 0xCC440104
29 #define CONFIG_SYS_DDR_TIMING_1_1000 0x727DF944
30 #define CONFIG_SYS_DDR_TIMING_2_1000 0x0FB088CF
31 #define CONFIG_SYS_DDR_MODE_1_1000 0x00441830
32 #define CONFIG_SYS_DDR_MODE_2_1000 0x00080000
33 #define CONFIG_SYS_DDR_INTERVAL_1000 0x0F3C0100
34 #define CONFIG_SYS_DDR_CLK_CTRL_1000 0x02800000
36 #define CONFIG_SYS_DDR_TIMING_3_900 0x00020000
37 #define CONFIG_SYS_DDR_TIMING_0_900 0xCC440104
38 #define CONFIG_SYS_DDR_TIMING_1_900 0x616ba844
39 #define CONFIG_SYS_DDR_TIMING_2_900 0x0fb088ce
40 #define CONFIG_SYS_DDR_MODE_1_900 0x00441620
41 #define CONFIG_SYS_DDR_MODE_2_900 0x00080000
42 #define CONFIG_SYS_DDR_INTERVAL_900 0x0db60100
43 #define CONFIG_SYS_DDR_CLK_CTRL_900 0x02800000
45 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000
46 #define CONFIG_SYS_DDR_TIMING_0_800 0xcc330104
47 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b4744
48 #define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cc
49 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420
50 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000
51 #define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100
52 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000
54 #define CONFIG_SYS_DDR_CS0_BNDS 0x000000FF
55 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
56 #define CONFIG_SYS_DDR_CS2_BNDS 0x000000FF
57 #define CONFIG_SYS_DDR_CS3_BNDS 0x000000FF
58 #define CONFIG_SYS_DDR2_CS0_BNDS 0x000000FF
59 #define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000
60 #define CONFIG_SYS_DDR2_CS2_BNDS 0x000000FF
61 #define CONFIG_SYS_DDR2_CS3_BNDS 0x000000FF
62 #define CONFIG_SYS_DDR_CS0_CONFIG 0xA0044202
63 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
64 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202
65 #define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000
66 #define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000
67 #define CONFIG_SYS_DDR2_CS0_CONFIG 0x80044202
68 #define CONFIG_SYS_DDR2_CS1_CONFIG 0x80004202
69 #define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000
70 #define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000
71 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
72 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
73 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202
74 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
75 #define CONFIG_SYS_DDR_TIMING_4 0x00000001
76 #define CONFIG_SYS_DDR_TIMING_5 0x02401400
77 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
78 #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
79 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607
80 #define CONFIG_SYS_DDR_SDRAM_CFG 0xE7044000
81 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x24401031
82 #define CONFIG_SYS_DDR_RCW_1 0x00000000
83 #define CONFIG_SYS_DDR_RCW_2 0x00000000
84 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
86 fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
87 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
88 .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
89 .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
90 .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
91 .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
92 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
93 .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
94 .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
95 .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
96 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
97 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
98 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
99 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
100 .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
101 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
102 .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
103 .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
104 .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
105 .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
106 .ddr_data_init = CONFIG_MEM_INIT_VALUE,
107 .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
108 .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
109 .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
110 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
111 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
112 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
113 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
114 .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
115 .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
118 fsl_ddr_cfg_regs_t ddr_cfg_regs_800_2nd = {
119 .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
120 .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
121 .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
122 .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
123 .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
124 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
125 .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
126 .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
127 .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
128 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
129 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
130 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
131 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
132 .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
133 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
134 .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
135 .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
136 .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
137 .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
138 .ddr_data_init = CONFIG_MEM_INIT_VALUE,
139 .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
140 .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
141 .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
142 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
143 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
144 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
145 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
146 .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
147 .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
150 fsl_ddr_cfg_regs_t ddr_cfg_regs_900 = {
151 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
152 .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
153 .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
154 .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
155 .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
156 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
157 .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
158 .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
159 .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
160 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900,
161 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900,
162 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900,
163 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900,
164 .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
165 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
166 .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900,
167 .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900,
168 .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
169 .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900,
170 .ddr_data_init = CONFIG_MEM_INIT_VALUE,
171 .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900,
172 .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
173 .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
174 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
175 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
176 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
177 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
178 .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
179 .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
182 fsl_ddr_cfg_regs_t ddr_cfg_regs_900_2nd = {
183 .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
184 .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
185 .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
186 .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
187 .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
188 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
189 .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
190 .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
191 .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
192 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900,
193 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900,
194 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900,
195 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900,
196 .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
197 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
198 .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900,
199 .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900,
200 .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
201 .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900,
202 .ddr_data_init = CONFIG_MEM_INIT_VALUE,
203 .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900,
204 .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
205 .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
206 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
207 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
208 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
209 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
210 .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
211 .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
214 fsl_ddr_cfg_regs_t ddr_cfg_regs_1000 = {
215 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
216 .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
217 .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
218 .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
219 .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
220 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
221 .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
222 .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
223 .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
224 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000,
225 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000,
226 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000,
227 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000,
228 .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
229 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
230 .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000,
231 .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000,
232 .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
233 .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000,
234 .ddr_data_init = CONFIG_MEM_INIT_VALUE,
235 .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000,
236 .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
237 .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
238 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
239 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
240 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
241 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
242 .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
243 .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
246 fsl_ddr_cfg_regs_t ddr_cfg_regs_1000_2nd = {
247 .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
248 .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
249 .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
250 .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
251 .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
252 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
253 .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
254 .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
255 .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
256 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000,
257 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000,
258 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000,
259 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000,
260 .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
261 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
262 .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000,
263 .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000,
264 .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
265 .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000,
266 .ddr_data_init = CONFIG_MEM_INIT_VALUE,
267 .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000,
268 .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
269 .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
270 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
271 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
272 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
273 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
274 .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
275 .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
278 fsl_ddr_cfg_regs_t ddr_cfg_regs_1200 = {
279 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
280 .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
281 .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
282 .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
283 .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
284 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
285 .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
286 .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
287 .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
288 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200,
289 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200,
290 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200,
291 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200,
292 .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
293 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
294 .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200,
295 .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200,
296 .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
297 .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200,
298 .ddr_data_init = CONFIG_MEM_INIT_VALUE,
299 .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200,
300 .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
301 .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
302 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
303 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
304 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
305 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
306 .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
307 .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
310 fsl_ddr_cfg_regs_t ddr_cfg_regs_1200_2nd = {
311 .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
312 .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
313 .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
314 .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
315 .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
316 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
317 .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
318 .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
319 .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
320 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200,
321 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200,
322 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200,
323 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200,
324 .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
325 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
326 .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200,
327 .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200,
328 .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
329 .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200,
330 .ddr_data_init = CONFIG_MEM_INIT_VALUE,
331 .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200,
332 .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
333 .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
334 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
335 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
336 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
337 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
338 .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
339 .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
342 fixed_ddr_parm_t fixed_ddr_parm_0[] = {
343 {DATARATE_800MHZ, DATARATE_900MHZ, &ddr_cfg_regs_800},
344 {DATARATE_900MHZ, DATARATE_1000MHZ, &ddr_cfg_regs_900},
345 {DATARATE_1000MHZ, DATARATE_1200MHZ, &ddr_cfg_regs_1000},
346 {DATARATE_1200MHZ, DATARATE_1300MHZ, &ddr_cfg_regs_1200},
350 fixed_ddr_parm_t fixed_ddr_parm_1[] = {
351 {DATARATE_800MHZ, DATARATE_900MHZ, &ddr_cfg_regs_800_2nd},
352 {DATARATE_900MHZ, DATARATE_1000MHZ, &ddr_cfg_regs_900_2nd},
353 {DATARATE_1000MHZ, DATARATE_1200MHZ, &ddr_cfg_regs_1000_2nd},
354 {DATARATE_1200MHZ, DATARATE_1300MHZ, &ddr_cfg_regs_1200_2nd},