2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/processor.h>
28 #include <asm/cache.h>
29 #include <asm/immap_85xx.h>
30 #include <asm/fsl_law.h>
31 #include <asm/fsl_ddr_sdram.h>
32 #include <asm/fsl_serdes.h>
33 #include <asm/fsl_portals.h>
34 #include <asm/fsl_liodn.h>
41 #include "../common/ngpixis.h"
42 #include "../common/fman.h"
43 #include <asm/fsl_dtsec.h>
45 #define EMI_NONE 0xffffffff
46 #define EMI_MASK 0xf0000000
47 #define EMI1_RGMII 0x0
48 #define EMI1_SLOT3 0x80000000 /* bank1 EFGH */
49 #define EMI1_SLOT4 0x40000000 /* bank2 ABCD */
50 #define EMI1_SLOT5 0xc0000000 /* bank3 ABCD */
51 #define EMI2_SLOT4 0x10000000 /* bank2 ABCD */
52 #define EMI2_SLOT5 0x30000000 /* bank3 ABCD */
53 #define EMI1_MASK 0xc0000000
54 #define EMI2_MASK 0x30000000
56 static int mdio_mux[NUM_FM_PORTS];
58 static char *mdio_names[16] = {
71 static char *p4080ds_mdio_name_for_muxval(u32 muxval)
73 return mdio_names[(muxval & EMI_MASK) >> 28];
76 struct mii_dev *mii_dev_for_muxval(u32 muxval)
79 char *name = p4080ds_mdio_name_for_muxval(muxval);
82 printf("No bus for muxval %x\n", muxval);
86 bus = miiphy_get_dev_by_name(name);
89 printf("No bus by name %s\n", name);
96 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
97 int board_phy_config(struct phy_device *phydev)
100 * If this is the 10G PHY, and we switched it to fiber,
101 * we need to reset the serdes link for SERDES9
103 if ((phydev->port == PORT_FIBRE) && (phydev->drv->uid == 0x00a19410)) {
104 enum srds_prtcl device;
106 switch (phydev->addr) {
117 serdes_reset_rx(device);
124 struct p4080ds_mdio {
126 struct mii_dev *realbus;
129 static void p4080ds_mux_mdio(u32 muxval)
131 ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
132 uint gpioval = in_be32(&pgpio->gpdat) & ~(EMI_MASK);
135 out_be32(&pgpio->gpdat, gpioval);
138 static int p4080ds_mdio_read(struct mii_dev *bus, int addr, int devad,
141 struct p4080ds_mdio *priv = bus->priv;
143 p4080ds_mux_mdio(priv->muxval);
145 return priv->realbus->read(priv->realbus, addr, devad, regnum);
148 static int p4080ds_mdio_write(struct mii_dev *bus, int addr, int devad,
149 int regnum, u16 value)
151 struct p4080ds_mdio *priv = bus->priv;
153 p4080ds_mux_mdio(priv->muxval);
155 return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
158 static int p4080ds_mdio_reset(struct mii_dev *bus)
160 struct p4080ds_mdio *priv = bus->priv;
162 return priv->realbus->reset(priv->realbus);
165 static int p4080ds_mdio_init(char *realbusname, u32 muxval)
167 struct p4080ds_mdio *pmdio;
168 struct mii_dev *bus = mdio_alloc();
171 printf("Failed to allocate P4080DS MDIO bus\n");
175 pmdio = malloc(sizeof(*pmdio));
177 printf("Failed to allocate P4080DS private data\n");
182 bus->read = p4080ds_mdio_read;
183 bus->write = p4080ds_mdio_write;
184 bus->reset = p4080ds_mdio_reset;
185 sprintf(bus->name, p4080ds_mdio_name_for_muxval(muxval));
187 pmdio->realbus = miiphy_get_dev_by_name(realbusname);
189 if (!pmdio->realbus) {
190 printf("No bus with name %s\n", realbusname);
196 pmdio->muxval = muxval;
199 return mdio_register(bus);
203 * Sets the specified node's status to the value contained in "status"
204 * If the first character of the specified path is "/" then we use
205 * alias as a path. Otherwise, we look for an alias of that name
207 static void fdt_set_node_status(void *fdt, const char *alias,
210 const char *path = fdt_get_alias(fdt, alias);
215 do_fixup_by_path(fdt, path, "status", status, strlen(status) + 1, 1);
218 void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
219 enum fm_port port, int offset)
221 if (mdio_mux[port] == EMI1_RGMII)
222 fdt_set_phy_handle(blob, prop, pa, "phy_rgmii");
224 if (mdio_mux[port] == EMI1_SLOT3) {
225 int idx = port - FM2_DTSEC1 + 5;
228 sprintf(phy, "phy%d_slot3", idx);
230 fdt_set_phy_handle(blob, prop, pa, phy);
234 void fdt_fixup_board_enet(void *fdt)
239 * P4080DS can be configured in many different ways, supporting a number
240 * of combinations of ethernet devices and phy types. In order to
241 * have just one device tree for all of those configurations, we fix up
242 * the tree here. By default, the device tree configures FM1 and FM2
243 * for SGMII, and configures XAUI on both 10G interfaces. So we have
244 * a number of different variables to track:
246 * 1) Whether the device is configured at all. Whichever devices are
247 * not enabled should be disabled by setting the "status" property
249 * 2) What the PHY interface is. If this is an RGMII connection,
250 * we should change the "phy-connection-type" property to
252 * 3) Which PHY is being used. Because the MDIO buses are muxed,
253 * we need to redirect the "phy-handle" property to point at the
254 * PHY on the right slot/bus.
257 /* We've got six MDIO nodes that may or may not need to exist */
258 fdt_set_node_status(fdt, "emi1_slot3", "disabled");
259 fdt_set_node_status(fdt, "emi1_slot4", "disabled");
260 fdt_set_node_status(fdt, "emi1_slot5", "disabled");
261 fdt_set_node_status(fdt, "emi2_slot4", "disabled");
262 fdt_set_node_status(fdt, "emi2_slot5", "disabled");
264 for (i = 0; i < NUM_FM_PORTS; i++) {
265 switch (mdio_mux[i]) {
267 fdt_set_node_status(fdt, "emi1_slot3", "okay");
270 fdt_set_node_status(fdt, "emi1_slot4", "okay");
273 fdt_set_node_status(fdt, "emi1_slot5", "okay");
276 fdt_set_node_status(fdt, "emi2_slot4", "okay");
279 fdt_set_node_status(fdt, "emi2_slot5", "okay");
294 int board_eth_init(bd_t *bis)
296 #ifdef CONFIG_FMAN_ENET
297 ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
298 struct dtsec *tsec = (void *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR;
300 struct fsl_pq_mdio_info dtsec_mdio_info;
301 struct tgec_mdio_info tgec_mdio_info;
303 u8 lane_to_slot[] = {
304 SLOT1, /* 0 - Bank 1:A */
305 SLOT1, /* 1 - Bank 1:B */
306 SLOT2, /* 2 - Bank 1:C */
307 SLOT2, /* 3 - Bank 1:D */
308 SLOT3, /* 4 - Bank 1:E */
309 SLOT3, /* 5 - Bank 1:F */
310 SLOT3, /* 6 - Bank 1:G */
311 SLOT3, /* 7 - Bank 1:H */
312 SLOT6, /* 8 - Bank 1:I */
313 SLOT6, /* 9 - Bank 1:J */
314 SLOT4, /* 10 - Bank 2:A */
315 SLOT4, /* 11 - Bank 2:B */
316 SLOT4, /* 12 - Bank 2:C */
317 SLOT4, /* 13 - Bank 2:D */
318 SLOT5, /* 14 - Bank 3:A */
319 SLOT5, /* 15 - Bank 3:B */
320 SLOT5, /* 16 - Bank 3:C */
321 SLOT5, /* 17 - Bank 3:D */
325 * Set TBIPA on FM1@DTSEC1. This is needed for configurations
326 * where FM1@DTSEC1 isn't used directly, since it provides
327 * MDIO for other ports.
329 out_be32(&tsec->tbipa, CONFIG_SYS_TBIPA_VALUE);
331 /* Initialize the mdio_mux array so we can recognize empty elements */
332 for (i = 0; i < NUM_FM_PORTS; i++)
333 mdio_mux[i] = EMI_NONE;
335 /* The first 4 GPIOs are outputs to control MDIO bus muxing */
336 out_be32(&pgpio->gpdir, EMI_MASK);
338 dtsec_mdio_info.regs =
339 (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
340 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
342 /* Register the 1G MDIO bus */
343 fsl_pq_mdio_init(bis, &dtsec_mdio_info);
345 tgec_mdio_info.regs =
346 (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
347 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
349 /* Register the 10G MDIO bus */
350 fm_tgec_mdio_init(bis, &tgec_mdio_info);
352 /* Register the 6 muxing front-ends to the MDIO buses */
353 p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII);
354 p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
355 p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
356 p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
357 p4080ds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2_SLOT4);
358 p4080ds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2_SLOT5);
360 fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
361 fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
362 fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
363 fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
364 fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
366 #if (CONFIG_SYS_NUM_FMAN == 2)
367 fm_info_set_phy_address(FM2_DTSEC1, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR);
368 fm_info_set_phy_address(FM2_DTSEC2, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR);
369 fm_info_set_phy_address(FM2_DTSEC3, CONFIG_SYS_FM2_DTSEC3_PHY_ADDR);
370 fm_info_set_phy_address(FM2_DTSEC4, CONFIG_SYS_FM2_DTSEC4_PHY_ADDR);
371 fm_info_set_phy_address(FM2_10GEC1, CONFIG_SYS_FM2_10GEC1_PHY_ADDR);
374 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
375 int idx = i - FM1_DTSEC1, lane, slot;
376 switch (fm_info_get_enet_if(i)) {
377 case PHY_INTERFACE_MODE_SGMII:
378 lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
381 slot = lane_to_slot[lane];
384 mdio_mux[i] = EMI1_SLOT3;
386 mii_dev_for_muxval(mdio_mux[i]));
389 mdio_mux[i] = EMI1_SLOT4;
391 mii_dev_for_muxval(mdio_mux[i]));
394 mdio_mux[i] = EMI1_SLOT5;
396 mii_dev_for_muxval(mdio_mux[i]));
400 case PHY_INTERFACE_MODE_RGMII:
401 fm_info_set_phy_address(i, 0);
402 mdio_mux[i] = EMI1_RGMII;
404 mii_dev_for_muxval(mdio_mux[i]));
411 for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
412 int idx = i - FM1_10GEC1, lane, slot;
413 switch (fm_info_get_enet_if(i)) {
414 case PHY_INTERFACE_MODE_XGMII:
415 lane = serdes_get_first_lane(XAUI_FM1 + idx);
418 slot = lane_to_slot[lane];
421 mdio_mux[i] = EMI2_SLOT4;
423 mii_dev_for_muxval(mdio_mux[i]));
426 mdio_mux[i] = EMI2_SLOT5;
428 mii_dev_for_muxval(mdio_mux[i]));
437 #if (CONFIG_SYS_NUM_FMAN == 2)
438 for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
439 int idx = i - FM2_DTSEC1, lane, slot;
440 switch (fm_info_get_enet_if(i)) {
441 case PHY_INTERFACE_MODE_SGMII:
442 lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
445 slot = lane_to_slot[lane];
448 mdio_mux[i] = EMI1_SLOT3;
450 mii_dev_for_muxval(mdio_mux[i]));
453 mdio_mux[i] = EMI1_SLOT4;
455 mii_dev_for_muxval(mdio_mux[i]));
458 mdio_mux[i] = EMI1_SLOT5;
460 mii_dev_for_muxval(mdio_mux[i]));
464 case PHY_INTERFACE_MODE_RGMII:
465 fm_info_set_phy_address(i, 0);
466 mdio_mux[i] = EMI1_RGMII;
468 mii_dev_for_muxval(mdio_mux[i]));
475 for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
476 int idx = i - FM2_10GEC1, lane, slot;
477 switch (fm_info_get_enet_if(i)) {
478 case PHY_INTERFACE_MODE_XGMII:
479 lane = serdes_get_first_lane(XAUI_FM2 + idx);
482 slot = lane_to_slot[lane];
485 mdio_mux[i] = EMI2_SLOT4;
487 mii_dev_for_muxval(mdio_mux[i]));
490 mdio_mux[i] = EMI2_SLOT5;
492 mii_dev_for_muxval(mdio_mux[i]));
503 #endif /* CONFIG_FMAN_ENET */
505 return pci_eth_init(bis);