2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/processor.h>
28 #include <asm/cache.h>
29 #include <asm/immap_85xx.h>
30 #include <asm/fsl_law.h>
31 #include <asm/fsl_ddr_sdram.h>
32 #include <asm/fsl_serdes.h>
33 #include <asm/fsl_portals.h>
34 #include <asm/fsl_liodn.h>
41 #include "../common/ngpixis.h"
42 #include "../common/fman.h"
43 #include <asm/fsl_dtsec.h>
45 #define EMI_NONE 0xffffffff
46 #define EMI_MASK 0xf0000000
47 #define EMI1_RGMII 0x0
48 #define EMI1_SLOT3 0x80000000 /* bank1 EFGH */
49 #define EMI1_SLOT4 0x40000000 /* bank2 ABCD */
50 #define EMI1_SLOT5 0xc0000000 /* bank3 ABCD */
51 #define EMI2_SLOT4 0x10000000 /* bank2 ABCD */
52 #define EMI2_SLOT5 0x30000000 /* bank3 ABCD */
53 #define EMI1_MASK 0xc0000000
54 #define EMI2_MASK 0x30000000
56 static int mdio_mux[NUM_FM_PORTS];
58 static char *mdio_names[16] = {
72 * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means
73 * that the mapping must be determined dynamically, or that the lane maps to
74 * something other than a board slot.
76 static u8 lane_to_slot[] = {
77 1, 1, 2, 2, 3, 3, 3, 3, 6, 6, 4, 4, 4, 4, 5, 5, 5, 5
80 static char *p4080ds_mdio_name_for_muxval(u32 muxval)
82 return mdio_names[(muxval & EMI_MASK) >> 28];
85 struct mii_dev *mii_dev_for_muxval(u32 muxval)
88 char *name = p4080ds_mdio_name_for_muxval(muxval);
91 printf("No bus for muxval %x\n", muxval);
95 bus = miiphy_get_dev_by_name(name);
98 printf("No bus by name %s\n", name);
105 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9) && defined(CONFIG_PHY_TERANETICS)
106 int board_phy_config(struct phy_device *phydev)
108 if (phydev->drv->config)
109 phydev->drv->config(phydev);
110 if (phydev->drv->uid == PHY_UID_TN2020) {
111 unsigned long timeout = 1 * 1000; /* 1 seconds */
112 enum srds_prtcl device;
115 * Wait for the XAUI to come out of reset. This is when it
116 * starts transmitting alignment signals.
119 int reg = phy_read(phydev, MDIO_MMD_PHYXS, MDIO_CTRL1);
121 printf("TN2020: Error reading from PHY at "
122 "address %u\n", phydev->addr);
126 * Note that we've never actually seen
127 * MDIO_CTRL1_RESET set to 1.
129 if ((reg & MDIO_CTRL1_RESET) == 0)
135 printf("TN2020: Timeout waiting for PHY at address %u "
136 " to reset.\n", phydev->addr);
139 switch (phydev->addr) {
140 case CONFIG_SYS_FM1_10GEC1_PHY_ADDR:
143 case CONFIG_SYS_FM2_10GEC1_PHY_ADDR:
150 serdes_reset_rx(device);
157 struct p4080ds_mdio {
159 struct mii_dev *realbus;
162 static void p4080ds_mux_mdio(u32 muxval)
164 ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
165 uint gpioval = in_be32(&pgpio->gpdat) & ~(EMI_MASK);
168 out_be32(&pgpio->gpdat, gpioval);
171 static int p4080ds_mdio_read(struct mii_dev *bus, int addr, int devad,
174 struct p4080ds_mdio *priv = bus->priv;
176 p4080ds_mux_mdio(priv->muxval);
178 return priv->realbus->read(priv->realbus, addr, devad, regnum);
181 static int p4080ds_mdio_write(struct mii_dev *bus, int addr, int devad,
182 int regnum, u16 value)
184 struct p4080ds_mdio *priv = bus->priv;
186 p4080ds_mux_mdio(priv->muxval);
188 return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
191 static int p4080ds_mdio_reset(struct mii_dev *bus)
193 struct p4080ds_mdio *priv = bus->priv;
195 return priv->realbus->reset(priv->realbus);
198 static int p4080ds_mdio_init(char *realbusname, u32 muxval)
200 struct p4080ds_mdio *pmdio;
201 struct mii_dev *bus = mdio_alloc();
204 printf("Failed to allocate P4080DS MDIO bus\n");
208 pmdio = malloc(sizeof(*pmdio));
210 printf("Failed to allocate P4080DS private data\n");
215 bus->read = p4080ds_mdio_read;
216 bus->write = p4080ds_mdio_write;
217 bus->reset = p4080ds_mdio_reset;
218 sprintf(bus->name, p4080ds_mdio_name_for_muxval(muxval));
220 pmdio->realbus = miiphy_get_dev_by_name(realbusname);
222 if (!pmdio->realbus) {
223 printf("No bus with name %s\n", realbusname);
229 pmdio->muxval = muxval;
232 return mdio_register(bus);
235 void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
236 enum fm_port port, int offset)
238 if (mdio_mux[port] == EMI1_RGMII)
239 fdt_set_phy_handle(blob, prop, pa, "phy_rgmii");
241 if (mdio_mux[port] == EMI1_SLOT3) {
242 int idx = port - FM2_DTSEC1 + 5;
245 sprintf(phy, "phy%d_slot3", idx);
247 fdt_set_phy_handle(blob, prop, pa, phy);
251 void fdt_fixup_board_enet(void *fdt)
256 * P4080DS can be configured in many different ways, supporting a number
257 * of combinations of ethernet devices and phy types. In order to
258 * have just one device tree for all of those configurations, we fix up
259 * the tree here. By default, the device tree configures FM1 and FM2
260 * for SGMII, and configures XAUI on both 10G interfaces. So we have
261 * a number of different variables to track:
263 * 1) Whether the device is configured at all. Whichever devices are
264 * not enabled should be disabled by setting the "status" property
266 * 2) What the PHY interface is. If this is an RGMII connection,
267 * we should change the "phy-connection-type" property to
269 * 3) Which PHY is being used. Because the MDIO buses are muxed,
270 * we need to redirect the "phy-handle" property to point at the
271 * PHY on the right slot/bus.
274 /* We've got six MDIO nodes that may or may not need to exist */
275 fdt_status_disabled_by_alias(fdt, "emi1_slot3");
276 fdt_status_disabled_by_alias(fdt, "emi1_slot4");
277 fdt_status_disabled_by_alias(fdt, "emi1_slot5");
278 fdt_status_disabled_by_alias(fdt, "emi2_slot4");
279 fdt_status_disabled_by_alias(fdt, "emi2_slot5");
281 for (i = 0; i < NUM_FM_PORTS; i++) {
282 switch (mdio_mux[i]) {
284 fdt_status_okay_by_alias(fdt, "emi1_slot3");
287 fdt_status_okay_by_alias(fdt, "emi1_slot4");
290 fdt_status_okay_by_alias(fdt, "emi1_slot5");
293 fdt_status_okay_by_alias(fdt, "emi2_slot4");
296 fdt_status_okay_by_alias(fdt, "emi2_slot5");
302 int board_eth_init(bd_t *bis)
304 #ifdef CONFIG_FMAN_ENET
305 ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
307 struct fsl_pq_mdio_info dtsec_mdio_info;
308 struct tgec_mdio_info tgec_mdio_info;
310 /* Initialize the mdio_mux array so we can recognize empty elements */
311 for (i = 0; i < NUM_FM_PORTS; i++)
312 mdio_mux[i] = EMI_NONE;
314 /* The first 4 GPIOs are outputs to control MDIO bus muxing */
315 out_be32(&pgpio->gpdir, EMI_MASK);
317 dtsec_mdio_info.regs =
318 (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
319 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
321 /* Register the 1G MDIO bus */
322 fsl_pq_mdio_init(bis, &dtsec_mdio_info);
324 tgec_mdio_info.regs =
325 (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
326 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
328 /* Register the 10G MDIO bus */
329 fm_tgec_mdio_init(bis, &tgec_mdio_info);
331 /* Register the 6 muxing front-ends to the MDIO buses */
332 p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII);
333 p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
334 p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
335 p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
336 p4080ds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2_SLOT4);
337 p4080ds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2_SLOT5);
339 fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
340 fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
341 fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
342 fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
343 fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
345 #if (CONFIG_SYS_NUM_FMAN == 2)
346 fm_info_set_phy_address(FM2_DTSEC1, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR);
347 fm_info_set_phy_address(FM2_DTSEC2, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR);
348 fm_info_set_phy_address(FM2_DTSEC3, CONFIG_SYS_FM2_DTSEC3_PHY_ADDR);
349 fm_info_set_phy_address(FM2_DTSEC4, CONFIG_SYS_FM2_DTSEC4_PHY_ADDR);
350 fm_info_set_phy_address(FM2_10GEC1, CONFIG_SYS_FM2_10GEC1_PHY_ADDR);
353 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
354 int idx = i - FM1_DTSEC1, lane, slot;
355 switch (fm_info_get_enet_if(i)) {
356 case PHY_INTERFACE_MODE_SGMII:
357 lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
360 slot = lane_to_slot[lane];
363 mdio_mux[i] = EMI1_SLOT3;
365 mii_dev_for_muxval(mdio_mux[i]));
368 mdio_mux[i] = EMI1_SLOT4;
370 mii_dev_for_muxval(mdio_mux[i]));
373 mdio_mux[i] = EMI1_SLOT5;
375 mii_dev_for_muxval(mdio_mux[i]));
379 case PHY_INTERFACE_MODE_RGMII:
380 fm_info_set_phy_address(i, 0);
381 mdio_mux[i] = EMI1_RGMII;
383 mii_dev_for_muxval(mdio_mux[i]));
390 for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
391 int idx = i - FM1_10GEC1, lane, slot;
392 switch (fm_info_get_enet_if(i)) {
393 case PHY_INTERFACE_MODE_XGMII:
394 lane = serdes_get_first_lane(XAUI_FM1 + idx);
397 slot = lane_to_slot[lane];
400 mdio_mux[i] = EMI2_SLOT4;
402 mii_dev_for_muxval(mdio_mux[i]));
405 mdio_mux[i] = EMI2_SLOT5;
407 mii_dev_for_muxval(mdio_mux[i]));
416 #if (CONFIG_SYS_NUM_FMAN == 2)
417 for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
418 int idx = i - FM2_DTSEC1, lane, slot;
419 switch (fm_info_get_enet_if(i)) {
420 case PHY_INTERFACE_MODE_SGMII:
421 lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
424 slot = lane_to_slot[lane];
427 mdio_mux[i] = EMI1_SLOT3;
429 mii_dev_for_muxval(mdio_mux[i]));
432 mdio_mux[i] = EMI1_SLOT4;
434 mii_dev_for_muxval(mdio_mux[i]));
437 mdio_mux[i] = EMI1_SLOT5;
439 mii_dev_for_muxval(mdio_mux[i]));
443 case PHY_INTERFACE_MODE_RGMII:
444 fm_info_set_phy_address(i, 0);
445 mdio_mux[i] = EMI1_RGMII;
447 mii_dev_for_muxval(mdio_mux[i]));
454 for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
455 int idx = i - FM2_10GEC1, lane, slot;
456 switch (fm_info_get_enet_if(i)) {
457 case PHY_INTERFACE_MODE_XGMII:
458 lane = serdes_get_first_lane(XAUI_FM2 + idx);
461 slot = lane_to_slot[lane];
464 mdio_mux[i] = EMI2_SLOT4;
466 mii_dev_for_muxval(mdio_mux[i]));
469 mdio_mux[i] = EMI2_SLOT5;
471 mii_dev_for_muxval(mdio_mux[i]));
482 #endif /* CONFIG_FMAN_ENET */
484 return pci_eth_init(bis);