1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
8 #include <fdt_support.h>
12 #include <asm/processor.h>
13 #include <asm/cache.h>
14 #include <asm/immap_85xx.h>
15 #include <asm/fsl_law.h>
16 #include <fsl_ddr_sdram.h>
17 #include <asm/fsl_serdes.h>
18 #include <asm/fsl_portals.h>
19 #include <asm/fsl_liodn.h>
25 #include <linux/delay.h>
27 #include "../common/ngpixis.h"
28 #include "../common/fman.h"
29 #include <fsl_dtsec.h>
31 #define EMI_NONE 0xffffffff
32 #define EMI_MASK 0xf0000000
33 #define EMI1_RGMII 0x0
34 #define EMI1_SLOT3 0x80000000 /* bank1 EFGH */
35 #define EMI1_SLOT4 0x40000000 /* bank2 ABCD */
36 #define EMI1_SLOT5 0xc0000000 /* bank3 ABCD */
37 #define EMI2_SLOT4 0x10000000 /* bank2 ABCD */
38 #define EMI2_SLOT5 0x30000000 /* bank3 ABCD */
39 #define EMI1_MASK 0xc0000000
40 #define EMI2_MASK 0x30000000
42 #define PHY_BASE_ADDR 0x00
43 #define PHY_BASE_ADDR_SLOT5 0x10
45 static int mdio_mux[NUM_FM_PORTS];
47 static char *mdio_names[16] = {
61 * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means
62 * that the mapping must be determined dynamically, or that the lane maps to
63 * something other than a board slot.
65 static u8 lane_to_slot[] = {
66 1, 1, 2, 2, 3, 3, 3, 3, 6, 6, 4, 4, 4, 4, 5, 5, 5, 5
69 static char *p4080ds_mdio_name_for_muxval(u32 muxval)
71 return mdio_names[(muxval & EMI_MASK) >> 28];
74 struct mii_dev *mii_dev_for_muxval(u32 muxval)
77 char *name = p4080ds_mdio_name_for_muxval(muxval);
80 printf("No bus for muxval %x\n", muxval);
84 bus = miiphy_get_dev_by_name(name);
87 printf("No bus by name %s\n", name);
94 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9) && defined(CONFIG_PHY_TERANETICS)
95 int board_phy_config(struct phy_device *phydev)
97 if (phydev->drv->config)
98 phydev->drv->config(phydev);
99 if (phydev->drv->uid == PHY_UID_TN2020) {
100 unsigned long timeout = 1 * 1000; /* 1 seconds */
101 enum srds_prtcl device;
104 * Wait for the XAUI to come out of reset. This is when it
105 * starts transmitting alignment signals.
108 int reg = phy_read(phydev, MDIO_MMD_PHYXS, MDIO_CTRL1);
110 printf("TN2020: Error reading from PHY at "
111 "address %u\n", phydev->addr);
115 * Note that we've never actually seen
116 * MDIO_CTRL1_RESET set to 1.
118 if ((reg & MDIO_CTRL1_RESET) == 0)
124 printf("TN2020: Timeout waiting for PHY at address %u "
125 " to reset.\n", phydev->addr);
128 switch (phydev->addr) {
129 case CONFIG_SYS_FM1_10GEC1_PHY_ADDR:
132 case CONFIG_SYS_FM2_10GEC1_PHY_ADDR:
139 serdes_reset_rx(device);
146 struct p4080ds_mdio {
148 struct mii_dev *realbus;
151 static void p4080ds_mux_mdio(u32 muxval)
153 ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
154 uint gpioval = in_be32(&pgpio->gpdat) & ~(EMI_MASK);
157 out_be32(&pgpio->gpdat, gpioval);
160 static int p4080ds_mdio_read(struct mii_dev *bus, int addr, int devad,
163 struct p4080ds_mdio *priv = bus->priv;
165 p4080ds_mux_mdio(priv->muxval);
167 return priv->realbus->read(priv->realbus, addr, devad, regnum);
170 static int p4080ds_mdio_write(struct mii_dev *bus, int addr, int devad,
171 int regnum, u16 value)
173 struct p4080ds_mdio *priv = bus->priv;
175 p4080ds_mux_mdio(priv->muxval);
177 return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
180 static int p4080ds_mdio_reset(struct mii_dev *bus)
182 struct p4080ds_mdio *priv = bus->priv;
184 return priv->realbus->reset(priv->realbus);
187 static int p4080ds_mdio_init(char *realbusname, u32 muxval)
189 struct p4080ds_mdio *pmdio;
190 struct mii_dev *bus = mdio_alloc();
193 printf("Failed to allocate P4080DS MDIO bus\n");
197 pmdio = malloc(sizeof(*pmdio));
199 printf("Failed to allocate P4080DS private data\n");
204 bus->read = p4080ds_mdio_read;
205 bus->write = p4080ds_mdio_write;
206 bus->reset = p4080ds_mdio_reset;
207 sprintf(bus->name, p4080ds_mdio_name_for_muxval(muxval));
209 pmdio->realbus = miiphy_get_dev_by_name(realbusname);
211 if (!pmdio->realbus) {
212 printf("No bus with name %s\n", realbusname);
218 pmdio->muxval = muxval;
221 return mdio_register(bus);
224 void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
225 enum fm_port port, int offset)
227 if (mdio_mux[port] == EMI1_RGMII)
228 fdt_set_phy_handle(blob, prop, pa, "phy_rgmii");
230 if (mdio_mux[port] == EMI1_SLOT3) {
231 int idx = port - FM2_DTSEC1 + 5;
234 sprintf(phy, "phy%d_slot3", idx);
236 fdt_set_phy_handle(blob, prop, pa, phy);
240 void fdt_fixup_board_enet(void *fdt)
245 * P4080DS can be configured in many different ways, supporting a number
246 * of combinations of ethernet devices and phy types. In order to
247 * have just one device tree for all of those configurations, we fix up
248 * the tree here. By default, the device tree configures FM1 and FM2
249 * for SGMII, and configures XAUI on both 10G interfaces. So we have
250 * a number of different variables to track:
252 * 1) Whether the device is configured at all. Whichever devices are
253 * not enabled should be disabled by setting the "status" property
255 * 2) What the PHY interface is. If this is an RGMII connection,
256 * we should change the "phy-connection-type" property to
258 * 3) Which PHY is being used. Because the MDIO buses are muxed,
259 * we need to redirect the "phy-handle" property to point at the
260 * PHY on the right slot/bus.
263 /* We've got six MDIO nodes that may or may not need to exist */
264 fdt_status_disabled_by_alias(fdt, "emi1_slot3");
265 fdt_status_disabled_by_alias(fdt, "emi1_slot4");
266 fdt_status_disabled_by_alias(fdt, "emi1_slot5");
267 fdt_status_disabled_by_alias(fdt, "emi2_slot4");
268 fdt_status_disabled_by_alias(fdt, "emi2_slot5");
270 for (i = 0; i < NUM_FM_PORTS; i++) {
271 switch (mdio_mux[i]) {
273 fdt_status_okay_by_alias(fdt, "emi1_slot3");
276 fdt_status_okay_by_alias(fdt, "emi1_slot4");
279 fdt_status_okay_by_alias(fdt, "emi1_slot5");
282 fdt_status_okay_by_alias(fdt, "emi2_slot4");
285 fdt_status_okay_by_alias(fdt, "emi2_slot5");
291 int board_eth_init(struct bd_info *bis)
293 #ifdef CONFIG_FMAN_ENET
294 ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
296 struct fsl_pq_mdio_info dtsec_mdio_info;
297 struct tgec_mdio_info tgec_mdio_info;
300 /* Initialize the mdio_mux array so we can recognize empty elements */
301 for (i = 0; i < NUM_FM_PORTS; i++)
302 mdio_mux[i] = EMI_NONE;
304 /* The first 4 GPIOs are outputs to control MDIO bus muxing */
305 out_be32(&pgpio->gpdir, EMI_MASK);
307 dtsec_mdio_info.regs =
308 (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
309 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
311 /* Register the 1G MDIO bus */
312 fsl_pq_mdio_init(bis, &dtsec_mdio_info);
314 tgec_mdio_info.regs =
315 (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
316 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
318 /* Register the 10G MDIO bus */
319 fm_tgec_mdio_init(bis, &tgec_mdio_info);
321 /* Register the 6 muxing front-ends to the MDIO buses */
322 p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII);
323 p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
324 p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
325 p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
326 p4080ds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2_SLOT4);
327 p4080ds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2_SLOT5);
329 fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
330 fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
331 fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
332 fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
333 fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
335 #if (CONFIG_SYS_NUM_FMAN == 2)
336 fm_info_set_phy_address(FM2_DTSEC1, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR);
337 fm_info_set_phy_address(FM2_DTSEC2, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR);
338 fm_info_set_phy_address(FM2_DTSEC3, CONFIG_SYS_FM2_DTSEC3_PHY_ADDR);
339 fm_info_set_phy_address(FM2_DTSEC4, CONFIG_SYS_FM2_DTSEC4_PHY_ADDR);
340 fm_info_set_phy_address(FM2_10GEC1, CONFIG_SYS_FM2_10GEC1_PHY_ADDR);
343 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
344 int idx = i - FM1_DTSEC1, lane, slot;
345 switch (fm_info_get_enet_if(i)) {
346 case PHY_INTERFACE_MODE_SGMII:
347 lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
350 slot = lane_to_slot[lane];
353 mdio_mux[i] = EMI1_SLOT3;
355 mii_dev_for_muxval(mdio_mux[i]));
358 mdio_mux[i] = EMI1_SLOT4;
360 mii_dev_for_muxval(mdio_mux[i]));
363 mdio_mux[i] = EMI1_SLOT5;
365 mii_dev_for_muxval(mdio_mux[i]));
369 case PHY_INTERFACE_MODE_RGMII:
370 fm_info_set_phy_address(i, 0);
371 mdio_mux[i] = EMI1_RGMII;
373 mii_dev_for_muxval(mdio_mux[i]));
379 bus = mii_dev_for_muxval(EMI1_SLOT5);
380 set_sgmii_phy(bus, FM1_DTSEC1,
381 CONFIG_SYS_NUM_FM1_DTSEC, PHY_BASE_ADDR_SLOT5);
383 for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
384 int idx = i - FM1_10GEC1, lane, slot;
385 switch (fm_info_get_enet_if(i)) {
386 case PHY_INTERFACE_MODE_XGMII:
387 lane = serdes_get_first_lane(XAUI_FM1 + idx);
390 slot = lane_to_slot[lane];
393 mdio_mux[i] = EMI2_SLOT4;
395 mii_dev_for_muxval(mdio_mux[i]));
398 mdio_mux[i] = EMI2_SLOT5;
400 mii_dev_for_muxval(mdio_mux[i]));
409 #if (CONFIG_SYS_NUM_FMAN == 2)
410 for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
411 int idx = i - FM2_DTSEC1, lane, slot;
412 switch (fm_info_get_enet_if(i)) {
413 case PHY_INTERFACE_MODE_SGMII:
414 lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
417 slot = lane_to_slot[lane];
420 mdio_mux[i] = EMI1_SLOT3;
422 mii_dev_for_muxval(mdio_mux[i]));
425 mdio_mux[i] = EMI1_SLOT4;
427 mii_dev_for_muxval(mdio_mux[i]));
430 mdio_mux[i] = EMI1_SLOT5;
432 mii_dev_for_muxval(mdio_mux[i]));
436 case PHY_INTERFACE_MODE_RGMII:
437 fm_info_set_phy_address(i, 0);
438 mdio_mux[i] = EMI1_RGMII;
440 mii_dev_for_muxval(mdio_mux[i]));
447 bus = mii_dev_for_muxval(EMI1_SLOT3);
448 set_sgmii_phy(bus, FM2_DTSEC1, CONFIG_SYS_NUM_FM2_DTSEC, PHY_BASE_ADDR);
449 bus = mii_dev_for_muxval(EMI1_SLOT4);
450 set_sgmii_phy(bus, FM2_DTSEC1, CONFIG_SYS_NUM_FM2_DTSEC, PHY_BASE_ADDR);
452 for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
453 int idx = i - FM2_10GEC1, lane, slot;
454 switch (fm_info_get_enet_if(i)) {
455 case PHY_INTERFACE_MODE_XGMII:
456 lane = serdes_get_first_lane(XAUI_FM2 + idx);
459 slot = lane_to_slot[lane];
462 mdio_mux[i] = EMI2_SLOT4;
464 mii_dev_for_muxval(mdio_mux[i]));
467 mdio_mux[i] = EMI2_SLOT5;
469 mii_dev_for_muxval(mdio_mux[i]));
480 #endif /* CONFIG_FMAN_ENET */
482 return pci_eth_init(bis);