2 * Copyright 2009-2010 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
13 #include <asm/fsl_ddr_sdram.h>
14 #include <asm/fsl_ddr_dimm_params.h>
15 #include <asm/fsl_law.h>
17 DECLARE_GLOBAL_DATA_PTR;
19 extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
20 unsigned int ctrl_num);
24 * Fixed sdram init -- doesn't use serial presence detect.
26 extern fixed_ddr_parm_t fixed_ddr_parm_0[];
27 #if (CONFIG_NUM_DDR_CONTROLLERS == 2)
28 extern fixed_ddr_parm_t fixed_ddr_parm_1[];
31 phys_size_t fixed_sdram(void)
36 fsl_ddr_cfg_regs_t ddr_cfg_regs;
38 unsigned int lawbar1_target_id;
40 get_sys_info(&sysinfo);
41 printf("Configuring DDR for %s MT/s data rate\n",
42 strmhz(buf, sysinfo.freqDDRBus));
44 for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
45 if ((sysinfo.freqDDRBus > fixed_ddr_parm_0[i].min_freq) &&
46 (sysinfo.freqDDRBus <= fixed_ddr_parm_0[i].max_freq)) {
48 fixed_ddr_parm_0[i].ddr_settings,
49 sizeof(ddr_cfg_regs));
54 if (fixed_ddr_parm_0[i].max_freq == 0)
55 panic("Unsupported DDR data rate %s MT/s data rate\n",
56 strmhz(buf, sysinfo.freqDDRBus));
58 ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
59 fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
61 #if (CONFIG_NUM_DDR_CONTROLLERS == 2)
63 fixed_ddr_parm_1[i].ddr_settings,
64 sizeof(ddr_cfg_regs));
65 fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 1);
69 * setup laws for DDR. If not interleaving, presuming half memory on
70 * DDR1 and the other half on DDR2
72 if (fixed_ddr_parm_0[i].ddr_settings->cs[0].config & 0x20000000) {
73 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
75 LAW_TRGT_IF_DDR_INTRLV) < 0) {
76 printf("ERROR setting Local Access Windows for DDR\n");
80 #if (CONFIG_NUM_DDR_CONTROLLERS == 2)
81 /* We require both controllers have identical DIMMs */
82 lawbar1_target_id = LAW_TRGT_IF_DDR_1;
83 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
85 lawbar1_target_id) < 0) {
86 printf("ERROR setting Local Access Windows for DDR\n");
89 lawbar1_target_id = LAW_TRGT_IF_DDR_2;
90 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE + ddr_size / 2,
92 lawbar1_target_id) < 0) {
93 printf("ERROR setting Local Access Windows for DDR\n");
97 lawbar1_target_id = LAW_TRGT_IF_DDR_1;
98 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
100 lawbar1_target_id) < 0) {
101 printf("ERROR setting Local Access Windows for DDR\n");
109 static void get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address)
113 ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t));
115 debug("DDR: failed to read SPD from address %u\n", i2c_address);
116 memset(spd, 0, sizeof(ddr3_spd_eeprom_t));
120 unsigned int fsl_ddr_get_mem_data_rate(void)
122 return get_ddr_freq(0);
125 void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd,
126 unsigned int ctrl_num)
129 unsigned int i2c_address = 0;
131 for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
132 if (ctrl_num == 0 && i == 0)
133 i2c_address = SPD_EEPROM_ADDRESS1;
134 else if (ctrl_num == 1 && i == 0)
135 i2c_address = SPD_EEPROM_ADDRESS2;
137 get_spd(&(ctrl_dimms_spd[i]), i2c_address);
142 u32 datarate_mhz_low;
143 u32 datarate_mhz_high;
147 u32 write_data_delay;
149 } board_specific_parameters_t;
151 /* ranges for parameters:
152 * wr_data_delay = 0-6
158 /* XXX: these values need to be checked for all interleaving modes. */
159 /* XXX: No reliable dual-rank 800 MHz setting has been found. It may
160 * seem reliable, but errors will appear when memory intensive
162 /* XXX: Single rank at 800 MHz is OK. */
163 const board_specific_parameters_t board_specific_parameters[][30] = {
165 /* memory controller 0 */
166 /* lo| hi| num| clk| cpo|wrdata|2T */
167 /* mhz| mhz|ranks|adjst| | delay| */
168 { 0, 333, 4, 6, 7, 3, 0},
169 {334, 400, 4, 6, 9, 3, 0},
170 {401, 549, 4, 6, 11, 3, 0},
171 {550, 680, 4, 1, 10, 5, 0},
172 {681, 850, 4, 1, 12, 5, 0},
173 {851, 1050, 4, 1, 12, 5, 0},
174 {1051, 1250, 4, 1, 15, 4, 0},
175 {1251, 1350, 4, 1, 15, 4, 0},
176 { 0, 333, 2, 6, 7, 3, 0},
177 {334, 400, 2, 6, 9, 3, 0},
178 {401, 549, 2, 6, 11, 3, 0},
179 {550, 680, 2, 1, 10, 5, 0},
180 {681, 850, 2, 1, 12, 5, 0},
181 {851, 1050, 2, 1, 12, 5, 0},
182 {1051, 1250, 2, 1, 15, 4, 0},
183 {1251, 1350, 2, 1, 15, 4, 0},
184 { 0, 333, 1, 6, 7, 3, 0},
185 {334, 400, 1, 6, 9, 3, 0},
186 {401, 549, 1, 6, 11, 3, 0},
187 {550, 680, 1, 1, 10, 5, 0},
188 {681, 850, 1, 1, 12, 5, 0}
192 /* memory controller 1 */
193 /* lo| hi| num| clk| cpo|wrdata|2T */
194 /* mhz| mhz|ranks|adjst| | delay| */
195 { 0, 333, 4, 6, 7, 3, 0},
196 {334, 400, 4, 6, 9, 3, 0},
197 {401, 549, 4, 6, 11, 3, 0},
198 {550, 680, 4, 1, 10, 5, 0},
199 {681, 850, 4, 1, 12, 5, 0},
200 {851, 1050, 4, 1, 12, 5, 0},
201 {1051, 1250, 4, 1, 15, 4, 0},
202 {1251, 1350, 4, 1, 15, 4, 0},
203 { 0, 333, 2, 6, 7, 3, 0},
204 {334, 400, 2, 6, 9, 3, 0},
205 {401, 549, 2, 6, 11, 3, 0},
206 {550, 680, 2, 1, 11, 6, 0},
207 {681, 850, 2, 1, 13, 6, 0},
208 {851, 1050, 2, 1, 13, 6, 0},
209 {1051, 1250, 2, 1, 15, 4, 0},
210 {1251, 1350, 2, 1, 15, 4, 0},
211 { 0, 333, 1, 6, 7, 3, 0},
212 {334, 400, 1, 6, 9, 3, 0},
213 {401, 549, 1, 6, 11, 3, 0},
214 {550, 680, 1, 1, 11, 6, 0},
215 {681, 850, 1, 1, 13, 6, 0}
219 void fsl_ddr_board_options(memctl_options_t *popts,
220 dimm_params_t *pdimm,
221 unsigned int ctrl_num)
223 const board_specific_parameters_t *pbsp =
224 &(board_specific_parameters[ctrl_num][0]);
225 u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
226 sizeof(board_specific_parameters[0][0]);
230 /* set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
231 * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
232 * there are two dimms in the controller, set odt_rd_cfg to 3 and
233 * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
235 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
236 if (i&1) { /* odd CS */
237 popts->cs_local_opts[i].odt_rd_cfg = 0;
238 popts->cs_local_opts[i].odt_wr_cfg = 1;
239 } else { /* even CS */
240 if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
241 popts->cs_local_opts[i].odt_rd_cfg = 0;
242 popts->cs_local_opts[i].odt_wr_cfg = 1;
243 } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
244 popts->cs_local_opts[i].odt_rd_cfg = 3;
245 popts->cs_local_opts[i].odt_wr_cfg = 3;
250 /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
251 * freqency and n_banks specified in board_specific_parameters table.
253 ddr_freq = get_ddr_freq(0) / 1000000;
254 for (i = 0; i < num_params; i++) {
255 if (ddr_freq >= pbsp->datarate_mhz_low &&
256 ddr_freq <= pbsp->datarate_mhz_high &&
257 pdimm->n_ranks == pbsp->n_ranks) {
258 popts->cpo_override = 0xff; /* force auto CPO calibration */
259 popts->write_data_delay = 2;
260 popts->clk_adjust = 5; /* Force value to be 5/8 clock cycle */
261 popts->twoT_en = pbsp->force_2T;
267 * Factors to consider for half-strength driver enable:
268 * - number of DIMMs installed
270 popts->half_strength_driver_enable = 0;
272 * Write leveling override
274 popts->wrlvl_override = 1;
275 popts->wrlvl_sample = 0xa;
276 popts->wrlvl_start = 0x7;
278 * Rtt and Rtt_WR override
280 popts->rtt_override = 1;
281 popts->rtt_override_value = DDR3_RTT_120_OHM;
282 popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */
284 /* Enable ZQ calibration */
288 phys_size_t initdram(int board_type)
290 phys_size_t dram_size;
293 puts("Initializing....");
295 #ifdef CONFIG_DDR_SPD
296 /* if hwconfig is not enabled, or "sdram" is not defined, use spd */
297 if (hwconfig_sub("fsl_ddr", "sdram")) {
298 if (hwconfig_subarg_cmp("fsl_ddr", "sdram", "spd"))
300 else if (hwconfig_subarg_cmp("fsl_ddr", "sdram", "fixed"))
310 dram_size = fsl_ddr_sdram();
312 puts("using fixed parameters\n");
313 dram_size = fixed_sdram();
316 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
317 dram_size *= 0x100000;