2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <linux/compiler.h>
12 #include <asm/processor.h>
13 #include <asm/cache.h>
14 #include <asm/immap_85xx.h>
15 #include <asm/fsl_law.h>
16 #include <asm/fsl_serdes.h>
17 #include <asm/fsl_portals.h>
18 #include <asm/fsl_liodn.h>
21 #include "../common/ngpixis.h"
22 #include "corenet_ds.h"
24 DECLARE_GLOBAL_DATA_PTR;
29 struct cpu_type *cpu = gd->arch.cpu;
30 #if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) || \
31 defined(CONFIG_P5040DS)
34 static const char * const freq[] = {"100", "125", "156.25", "212.5" };
36 printf("Board: %sDS, ", cpu->name);
37 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
38 in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
40 sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
41 sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT;
44 printf("vBank: %d\n", sw);
50 printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH);
52 /* Display the actual SERDES reference clocks as configured by the
53 * dip switches on the board. Note that the SWx registers could
54 * technically be set to force the reference clocks to match the
55 * values that the SERDES expects (or vice versa). For now, however,
56 * we just display both values and hope the user notices when they
59 puts("SERDES Reference Clocks: ");
60 #if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) \
61 || defined(CONFIG_P5040DS)
62 sw = in_8(&PIXIS_SW(5));
63 for (i = 0; i < 3; i++) {
64 unsigned int clock = (sw >> (6 - (2 * i))) & 3;
66 printf("Bank%u=%sMhz ", i+1, freq[clock]);
69 /* On P5040DS, SW11[7:8] determines the Bank 4 frequency */
70 sw = in_8(&PIXIS_SW(9));
71 printf("Bank4=%sMhz ", freq[sw & 3]);
75 sw = in_8(&PIXIS_SW(3));
76 /* SW3[2]: 0 = 100 Mhz, 1 = 125 MHz */
77 /* SW3[3]: 0 = 125 Mhz, 1 = 156.25 MHz */
78 /* SW3[4]: 0 = 125 Mhz, 1 = 156.25 MHz */
79 printf("Bank1=%sMHz ", freq[!!(sw & 0x40)]);
80 printf("Bank2=%sMHz ", freq[1 + !!(sw & 0x20)]);
81 printf("Bank3=%sMHz\n", freq[1 + !!(sw & 0x10)]);
87 int board_early_init_f(void)
89 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
92 * P4080 DS board only uses the DDR1_MCK0/3 and DDR2_MCK0/3
93 * disable the DDR1_MCK1/2/4/5 and DDR2_MCK1/2/4/5 to reduce
94 * the noise introduced by these unterminated and unused clock pairs.
96 setbits_be32(&gur->ddrclkdr, 0x001B001B);
101 int board_early_init_r(void)
103 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
104 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
107 * Remap Boot flash + PROMJET region to caching-inhibited
108 * so that flash can be erased properly.
111 /* Flush d-cache and invalidate i-cache of any FLASH data */
115 /* invalidate existing TLB entry for flash + promjet */
116 disable_tlb(flash_esel);
118 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
119 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
120 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
123 #ifdef CONFIG_SYS_DPAA_QBMAN
130 static const char *serdes_clock_to_string(u32 clock)
133 case SRDS_PLLCR0_RFCK_SEL_100:
135 case SRDS_PLLCR0_RFCK_SEL_125:
137 case SRDS_PLLCR0_RFCK_SEL_156_25:
144 #define NUM_SRDS_BANKS 3
146 int misc_init_r(void)
148 serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
149 u32 actual[NUM_SRDS_BANKS];
153 #if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) \
154 || defined(CONFIG_P5040DS)
155 sw = in_8(&PIXIS_SW(5));
156 for (i = 0; i < 3; i++) {
157 unsigned int clock = (sw >> (6 - (2 * i))) & 3;
160 actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
163 actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
166 actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
169 printf("Warning: SDREFCLK%u switch setting of '11' is "
170 "unsupported\n", i + 1);
175 /* Warn if the expected SERDES reference clocks don't match the
176 * actual reference clocks. This needs to be done after calling
177 * p4080_erratum_serdes8(), since that function may modify the clocks.
179 sw = in_8(&PIXIS_SW(3));
180 actual[0] = (sw & 0x40) ?
181 SRDS_PLLCR0_RFCK_SEL_125 : SRDS_PLLCR0_RFCK_SEL_100;
182 actual[1] = (sw & 0x20) ?
183 SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125;
184 actual[2] = (sw & 0x10) ?
185 SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125;
188 for (i = 0; i < NUM_SRDS_BANKS; i++) {
189 u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
190 if (expected != actual[i]) {
191 printf("Warning: SERDES bank %u expects reference clock"
192 " %sMHz, but actual is %sMHz\n", i + 1,
193 serdes_clock_to_string(expected),
194 serdes_clock_to_string(actual[i]));
201 void ft_board_setup(void *blob, bd_t *bd)
206 ft_cpu_setup(blob, bd);
208 base = getenv_bootm_low();
209 size = getenv_bootm_size();
211 fdt_fixup_memory(blob, (u64)base, (u64)size);
214 pci_of_setup(blob, bd);
217 fdt_fixup_liodn(blob);
218 fdt_fixup_dr_usb(blob, bd);
220 #ifdef CONFIG_SYS_DPAA_FMAN
221 fdt_fixup_fman_ethernet(blob);
222 fdt_fixup_board_enet(blob);