1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
9 #include <fdt_support.h>
12 #include <linux/compiler.h>
14 #include <asm/processor.h>
15 #include <asm/cache.h>
16 #include <asm/immap_85xx.h>
17 #include <asm/fsl_law.h>
18 #include <asm/fsl_serdes.h>
19 #include <asm/fsl_liodn.h>
22 #include "../common/ngpixis.h"
23 #include "corenet_ds.h"
25 DECLARE_GLOBAL_DATA_PTR;
30 struct cpu_type *cpu = gd->arch.cpu;
31 #if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \
32 defined(CONFIG_TARGET_P5040DS)
35 static const char * const freq[] = {"100", "125", "156.25", "212.5" };
37 printf("Board: %sDS, ", cpu->name);
38 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
39 in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
41 sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
42 sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT;
45 printf("vBank: %d\n", sw);
51 printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH);
53 /* Display the actual SERDES reference clocks as configured by the
54 * dip switches on the board. Note that the SWx registers could
55 * technically be set to force the reference clocks to match the
56 * values that the SERDES expects (or vice versa). For now, however,
57 * we just display both values and hope the user notices when they
60 puts("SERDES Reference Clocks: ");
61 #if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \
62 defined(CONFIG_TARGET_P5040DS)
63 sw = in_8(&PIXIS_SW(5));
64 for (i = 0; i < 3; i++) {
65 unsigned int clock = (sw >> (6 - (2 * i))) & 3;
67 printf("Bank%u=%sMhz ", i+1, freq[clock]);
69 #ifdef CONFIG_TARGET_P5040DS
70 /* On P5040DS, SW11[7:8] determines the Bank 4 frequency */
71 sw = in_8(&PIXIS_SW(9));
72 printf("Bank4=%sMhz ", freq[sw & 3]);
76 sw = in_8(&PIXIS_SW(3));
77 /* SW3[2]: 0 = 100 Mhz, 1 = 125 MHz */
78 /* SW3[3]: 0 = 125 Mhz, 1 = 156.25 MHz */
79 /* SW3[4]: 0 = 125 Mhz, 1 = 156.25 MHz */
80 printf("Bank1=%sMHz ", freq[!!(sw & 0x40)]);
81 printf("Bank2=%sMHz ", freq[1 + !!(sw & 0x20)]);
82 printf("Bank3=%sMHz\n", freq[1 + !!(sw & 0x10)]);
88 int board_early_init_f(void)
90 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
93 * P4080 DS board only uses the DDR1_MCK0/3 and DDR2_MCK0/3
94 * disable the DDR1_MCK1/2/4/5 and DDR2_MCK1/2/4/5 to reduce
95 * the noise introduced by these unterminated and unused clock pairs.
97 setbits_be32(&gur->ddrclkdr, 0x001B001B);
102 int board_early_init_r(void)
104 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
105 int flash_esel = find_tlb_idx((void *)flashbase, 1);
108 * Remap Boot flash + PROMJET region to caching-inhibited
109 * so that flash can be erased properly.
112 /* Flush d-cache and invalidate i-cache of any FLASH data */
116 if (flash_esel == -1) {
117 /* very unlikely unless something is messed up */
118 puts("Error: Could not find TLB for FLASH BASE\n");
119 flash_esel = 2; /* give our best effort to continue */
121 /* invalidate existing TLB entry for flash + promjet */
122 disable_tlb(flash_esel);
125 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
126 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
127 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
132 #define NUM_SRDS_BANKS 3
134 int misc_init_r(void)
136 serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
137 u32 actual[NUM_SRDS_BANKS];
141 #if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \
142 defined(CONFIG_TARGET_P5040DS)
143 sw = in_8(&PIXIS_SW(5));
144 for (i = 0; i < 3; i++) {
145 unsigned int clock = (sw >> (6 - (2 * i))) & 3;
148 actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
151 actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
154 actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
157 printf("Warning: SDREFCLK%u switch setting of '11' is "
158 "unsupported\n", i + 1);
163 /* Warn if the expected SERDES reference clocks don't match the
164 * actual reference clocks. This needs to be done after calling
165 * p4080_erratum_serdes8(), since that function may modify the clocks.
167 sw = in_8(&PIXIS_SW(3));
168 actual[0] = (sw & 0x40) ?
169 SRDS_PLLCR0_RFCK_SEL_125 : SRDS_PLLCR0_RFCK_SEL_100;
170 actual[1] = (sw & 0x20) ?
171 SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125;
172 actual[2] = (sw & 0x10) ?
173 SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125;
176 for (i = 0; i < NUM_SRDS_BANKS; i++) {
177 u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
178 if (expected != actual[i]) {
179 printf("Warning: SERDES bank %u expects reference clock"
180 " %sMHz, but actual is %sMHz\n", i + 1,
181 serdes_clock_to_string(expected),
182 serdes_clock_to_string(actual[i]));
189 int ft_board_setup(void *blob, bd_t *bd)
194 ft_cpu_setup(blob, bd);
196 base = env_get_bootm_low();
197 size = env_get_bootm_size();
199 fdt_fixup_memory(blob, (u64)base, (u64)size);
202 pci_of_setup(blob, bd);
205 fdt_fixup_liodn(blob);
206 fsl_fdt_fixup_dr_usb(blob, bd);
208 #ifdef CONFIG_SYS_DPAA_FMAN
209 fdt_fixup_fman_ethernet(blob);
210 fdt_fixup_board_enet(blob);