2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <linux/compiler.h>
12 #include <asm/processor.h>
13 #include <asm/cache.h>
14 #include <asm/immap_85xx.h>
15 #include <asm/fsl_law.h>
16 #include <asm/fsl_serdes.h>
17 #include <asm/fsl_liodn.h>
20 #include "../common/ngpixis.h"
21 #include "corenet_ds.h"
23 DECLARE_GLOBAL_DATA_PTR;
28 struct cpu_type *cpu = gd->arch.cpu;
29 #if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) || \
30 defined(CONFIG_P5040DS)
33 static const char * const freq[] = {"100", "125", "156.25", "212.5" };
35 printf("Board: %sDS, ", cpu->name);
36 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
37 in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
39 sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
40 sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT;
43 printf("vBank: %d\n", sw);
49 printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH);
51 /* Display the actual SERDES reference clocks as configured by the
52 * dip switches on the board. Note that the SWx registers could
53 * technically be set to force the reference clocks to match the
54 * values that the SERDES expects (or vice versa). For now, however,
55 * we just display both values and hope the user notices when they
58 puts("SERDES Reference Clocks: ");
59 #if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) \
60 || defined(CONFIG_P5040DS)
61 sw = in_8(&PIXIS_SW(5));
62 for (i = 0; i < 3; i++) {
63 unsigned int clock = (sw >> (6 - (2 * i))) & 3;
65 printf("Bank%u=%sMhz ", i+1, freq[clock]);
68 /* On P5040DS, SW11[7:8] determines the Bank 4 frequency */
69 sw = in_8(&PIXIS_SW(9));
70 printf("Bank4=%sMhz ", freq[sw & 3]);
74 sw = in_8(&PIXIS_SW(3));
75 /* SW3[2]: 0 = 100 Mhz, 1 = 125 MHz */
76 /* SW3[3]: 0 = 125 Mhz, 1 = 156.25 MHz */
77 /* SW3[4]: 0 = 125 Mhz, 1 = 156.25 MHz */
78 printf("Bank1=%sMHz ", freq[!!(sw & 0x40)]);
79 printf("Bank2=%sMHz ", freq[1 + !!(sw & 0x20)]);
80 printf("Bank3=%sMHz\n", freq[1 + !!(sw & 0x10)]);
86 int board_early_init_f(void)
88 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
91 * P4080 DS board only uses the DDR1_MCK0/3 and DDR2_MCK0/3
92 * disable the DDR1_MCK1/2/4/5 and DDR2_MCK1/2/4/5 to reduce
93 * the noise introduced by these unterminated and unused clock pairs.
95 setbits_be32(&gur->ddrclkdr, 0x001B001B);
100 int board_early_init_r(void)
102 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
103 int flash_esel = find_tlb_idx((void *)flashbase, 1);
106 * Remap Boot flash + PROMJET region to caching-inhibited
107 * so that flash can be erased properly.
110 /* Flush d-cache and invalidate i-cache of any FLASH data */
114 if (flash_esel == -1) {
115 /* very unlikely unless something is messed up */
116 puts("Error: Could not find TLB for FLASH BASE\n");
117 flash_esel = 2; /* give our best effort to continue */
119 /* invalidate existing TLB entry for flash + promjet */
120 disable_tlb(flash_esel);
123 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
124 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
125 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
130 #define NUM_SRDS_BANKS 3
132 int misc_init_r(void)
134 serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
135 u32 actual[NUM_SRDS_BANKS];
139 #if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) \
140 || defined(CONFIG_P5040DS)
141 sw = in_8(&PIXIS_SW(5));
142 for (i = 0; i < 3; i++) {
143 unsigned int clock = (sw >> (6 - (2 * i))) & 3;
146 actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
149 actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
152 actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
155 printf("Warning: SDREFCLK%u switch setting of '11' is "
156 "unsupported\n", i + 1);
161 /* Warn if the expected SERDES reference clocks don't match the
162 * actual reference clocks. This needs to be done after calling
163 * p4080_erratum_serdes8(), since that function may modify the clocks.
165 sw = in_8(&PIXIS_SW(3));
166 actual[0] = (sw & 0x40) ?
167 SRDS_PLLCR0_RFCK_SEL_125 : SRDS_PLLCR0_RFCK_SEL_100;
168 actual[1] = (sw & 0x20) ?
169 SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125;
170 actual[2] = (sw & 0x10) ?
171 SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125;
174 for (i = 0; i < NUM_SRDS_BANKS; i++) {
175 u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
176 if (expected != actual[i]) {
177 printf("Warning: SERDES bank %u expects reference clock"
178 " %sMHz, but actual is %sMHz\n", i + 1,
179 serdes_clock_to_string(expected),
180 serdes_clock_to_string(actual[i]));
187 int ft_board_setup(void *blob, bd_t *bd)
192 ft_cpu_setup(blob, bd);
194 base = getenv_bootm_low();
195 size = getenv_bootm_size();
197 fdt_fixup_memory(blob, (u64)base, (u64)size);
200 pci_of_setup(blob, bd);
203 fdt_fixup_liodn(blob);
204 fdt_fixup_dr_usb(blob, bd);
206 #ifdef CONFIG_SYS_DPAA_FMAN
207 fdt_fixup_fman_ethernet(blob);
208 fdt_fixup_board_enet(blob);