1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2011 Freescale Semiconductor
5 * Author: Shengzhou Liu <Shengzhou.Liu@freescale.com>
7 * This file provides support for the QIXIS of some Freescale reference boards.
13 #include <linux/compiler.h>
14 #include <linux/time.h>
18 #ifndef QIXIS_LBMAP_BRDCFG_REG
20 * For consistency with existing platforms
22 #define QIXIS_LBMAP_BRDCFG_REG 0x00
25 #ifndef QIXIS_RCFG_CTL_RECONFIG_IDLE
26 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
28 #ifndef QIXIS_RCFG_CTL_RECONFIG_START
29 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
32 #ifdef CONFIG_SYS_I2C_FPGA_ADDR
33 u8 qixis_read_i2c(unsigned int reg)
36 return i2c_reg_read(CONFIG_SYS_I2C_FPGA_ADDR, reg);
40 if (i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev))
43 return dm_i2c_reg_read(dev, reg);
47 void qixis_write_i2c(unsigned int reg, u8 value)
51 i2c_reg_write(CONFIG_SYS_I2C_FPGA_ADDR, reg, val);
55 if (!i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev))
56 dm_i2c_reg_write(dev, reg, val);
63 u8 qixis_read(unsigned int reg)
65 void *p = (void *)QIXIS_BASE;
70 void qixis_write(unsigned int reg, u8 value)
72 void *p = (void *)QIXIS_BASE;
74 out_8(p + reg, value);
78 u16 qixis_read_minor(void)
82 /* this data is in little endian */
83 QIXIS_WRITE(tagdata, 5);
84 minor = QIXIS_READ(tagdata);
85 QIXIS_WRITE(tagdata, 6);
86 minor += QIXIS_READ(tagdata) << 8;
91 char *qixis_read_time(char *result)
96 /* timestamp is in 32-bit big endian */
97 for (i = 8; i <= 11; i++) {
98 QIXIS_WRITE(tagdata, i);
99 time = (time << 8) + QIXIS_READ(tagdata);
102 return ctime_r(&time, result);
105 char *qixis_read_tag(char *buf)
108 char tag, *ptr = buf;
110 for (i = 16; i <= 63; i++) {
111 QIXIS_WRITE(tagdata, i);
112 tag = QIXIS_READ(tagdata);
124 * return the string of binary of u8 in the format of
125 * 1010 10_0. The masked bit is filled as underscore.
127 const char *byte_to_binary_mask(u8 val, u8 mask, char *buf)
133 for (i = 0x80; i > 0x08 ; i >>= 1, ptr++)
134 *ptr = (val & i) ? '1' : ((mask & i) ? '_' : '0');
136 for (i = 0x08; i > 0 ; i >>= 1, ptr++)
137 *ptr = (val & i) ? '1' : ((mask & i) ? '_' : '0');
144 #ifdef QIXIS_RST_FORCE_MEM
145 void board_assert_mem_reset(void)
149 rst = QIXIS_READ(rst_frc[0]);
150 if (!(rst & QIXIS_RST_FORCE_MEM))
151 QIXIS_WRITE(rst_frc[0], rst | QIXIS_RST_FORCE_MEM);
154 void board_deassert_mem_reset(void)
158 rst = QIXIS_READ(rst_frc[0]);
159 if (rst & QIXIS_RST_FORCE_MEM)
160 QIXIS_WRITE(rst_frc[0], rst & ~QIXIS_RST_FORCE_MEM);
164 #ifndef CONFIG_SPL_BUILD
165 static void qixis_reset(void)
167 QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET);
170 #ifdef QIXIS_LBMAP_ALTBANK
171 static void qixis_bank_reset(void)
173 QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
174 QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
178 static void __maybe_unused set_lbmap(int lbmap)
182 reg = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
183 reg = (reg & ~QIXIS_LBMAP_MASK) | lbmap;
184 QIXIS_WRITE(brdcfg[QIXIS_LBMAP_BRDCFG_REG], reg);
187 static void __maybe_unused set_rcw_src(int rcw_src)
189 #ifdef CONFIG_NXP_LSCH3_2
190 QIXIS_WRITE(dutcfg[0], (rcw_src & 0xff));
194 reg = QIXIS_READ(dutcfg[1]);
195 reg = (reg & ~1) | (rcw_src & 1);
196 QIXIS_WRITE(dutcfg[1], reg);
197 QIXIS_WRITE(dutcfg[0], (rcw_src >> 1) & 0xff);
201 static void qixis_dump_regs(void)
205 printf("id = %02x\n", QIXIS_READ(id));
206 printf("arch = %02x\n", QIXIS_READ(arch));
207 printf("scver = %02x\n", QIXIS_READ(scver));
208 printf("model = %02x\n", QIXIS_READ(model));
209 printf("rst_ctl = %02x\n", QIXIS_READ(rst_ctl));
210 printf("aux = %02x\n", QIXIS_READ(aux));
211 for (i = 0; i < 16; i++)
212 printf("brdcfg%02d = %02x\n", i, QIXIS_READ(brdcfg[i]));
213 for (i = 0; i < 16; i++)
214 printf("dutcfg%02d = %02x\n", i, QIXIS_READ(dutcfg[i]));
215 printf("sclk = %02x%02x%02x\n", QIXIS_READ(sclk[0]),
216 QIXIS_READ(sclk[1]), QIXIS_READ(sclk[2]));
217 printf("dclk = %02x%02x%02x\n", QIXIS_READ(dclk[0]),
218 QIXIS_READ(dclk[1]), QIXIS_READ(dclk[2]));
219 printf("aux = %02x\n", QIXIS_READ(aux));
220 printf("watch = %02x\n", QIXIS_READ(watch));
221 printf("ctl_sys = %02x\n", QIXIS_READ(ctl_sys));
222 printf("rcw_ctl = %02x\n", QIXIS_READ(rcw_ctl));
223 printf("present = %02x\n", QIXIS_READ(present));
224 printf("present2 = %02x\n", QIXIS_READ(present2));
225 printf("clk_spd = %02x\n", QIXIS_READ(clk_spd));
226 printf("stat_dut = %02x\n", QIXIS_READ(stat_dut));
227 printf("stat_sys = %02x\n", QIXIS_READ(stat_sys));
228 printf("stat_alrm = %02x\n", QIXIS_READ(stat_alrm));
231 void __weak qixis_dump_switch(void)
233 puts("Reverse engineering switch is not implemented for this board\n");
236 static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
241 set_lbmap(QIXIS_LBMAP_DFLTBANK);
243 } else if (strcmp(argv[1], "altbank") == 0) {
244 #ifdef QIXIS_LBMAP_ALTBANK
245 set_lbmap(QIXIS_LBMAP_ALTBANK);
248 printf("No Altbank!\n");
250 } else if (strcmp(argv[1], "nand") == 0) {
251 #ifdef QIXIS_LBMAP_NAND
252 QIXIS_WRITE(rst_ctl, 0x30);
253 QIXIS_WRITE(rcfg_ctl, 0);
254 set_lbmap(QIXIS_LBMAP_NAND);
255 set_rcw_src(QIXIS_RCW_SRC_NAND);
256 QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
257 QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
259 printf("Not implemented\n");
261 } else if (strcmp(argv[1], "sd") == 0) {
262 #ifdef QIXIS_LBMAP_SD
263 QIXIS_WRITE(rst_ctl, 0x30);
264 QIXIS_WRITE(rcfg_ctl, 0);
265 #ifdef NON_EXTENDED_DUTCFG
266 QIXIS_WRITE(dutcfg[0], QIXIS_RCW_SRC_SD);
268 set_lbmap(QIXIS_LBMAP_SD);
269 set_rcw_src(QIXIS_RCW_SRC_SD);
271 QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
272 QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
274 printf("Not implemented\n");
276 } else if (strcmp(argv[1], "ifc") == 0) {
277 #ifdef QIXIS_LBMAP_IFC
278 QIXIS_WRITE(rst_ctl, 0x30);
279 QIXIS_WRITE(rcfg_ctl, 0);
280 set_lbmap(QIXIS_LBMAP_IFC);
281 set_rcw_src(QIXIS_RCW_SRC_IFC);
282 QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
283 QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
285 printf("Not implemented\n");
287 } else if (strcmp(argv[1], "emmc") == 0) {
288 #ifdef QIXIS_LBMAP_EMMC
289 QIXIS_WRITE(rst_ctl, 0x30);
290 QIXIS_WRITE(rcfg_ctl, 0);
291 #ifndef NON_EXTENDED_DUTCFG
292 set_lbmap(QIXIS_LBMAP_EMMC);
294 set_rcw_src(QIXIS_RCW_SRC_EMMC);
295 QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
296 QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
298 printf("Not implemented\n");
300 } else if (strcmp(argv[1], "sd_qspi") == 0) {
301 #ifdef QIXIS_LBMAP_SD_QSPI
302 QIXIS_WRITE(rst_ctl, 0x30);
303 QIXIS_WRITE(rcfg_ctl, 0);
304 set_lbmap(QIXIS_LBMAP_SD_QSPI);
305 set_rcw_src(QIXIS_RCW_SRC_SD);
306 qixis_write_i2c(offsetof(struct qixis, rcfg_ctl),
307 QIXIS_RCFG_CTL_RECONFIG_IDLE);
308 qixis_write_i2c(offsetof(struct qixis, rcfg_ctl),
309 QIXIS_RCFG_CTL_RECONFIG_START);
311 printf("Not implemented\n");
313 } else if (strcmp(argv[1], "qspi") == 0) {
314 #ifdef QIXIS_LBMAP_QSPI
315 QIXIS_WRITE(rst_ctl, 0x30);
316 QIXIS_WRITE(rcfg_ctl, 0);
317 set_lbmap(QIXIS_LBMAP_QSPI);
318 set_rcw_src(QIXIS_RCW_SRC_QSPI);
319 qixis_write_i2c(offsetof(struct qixis, rcfg_ctl),
320 QIXIS_RCFG_CTL_RECONFIG_IDLE);
321 qixis_write_i2c(offsetof(struct qixis, rcfg_ctl),
322 QIXIS_RCFG_CTL_RECONFIG_START);
324 printf("Not implemented\n");
326 } else if (strcmp(argv[1], "watchdog") == 0) {
327 static char *period[9] = {"2s", "4s", "8s", "16s", "32s",
328 "1min", "2min", "4min", "8min"};
329 u8 rcfg = QIXIS_READ(rcfg_ctl);
331 if (argv[2] == NULL) {
332 printf("qixis watchdog <watchdog_period>\n");
335 for (i = 0; i < ARRAY_SIZE(period); i++) {
336 if (strcmp(argv[2], period[i]) == 0) {
337 /* disable watchdog */
338 QIXIS_WRITE(rcfg_ctl,
339 rcfg & ~QIXIS_RCFG_CTL_WATCHDOG_ENBLE);
340 QIXIS_WRITE(watch, ((i<<2) - 1));
341 QIXIS_WRITE(rcfg_ctl, rcfg);
345 } else if (strcmp(argv[1], "dump") == 0) {
348 } else if (strcmp(argv[1], "switch") == 0) {
352 printf("Invalid option: %s\n", argv[1]);
360 qixis_reset, CONFIG_SYS_MAXARGS, 1, qixis_reset_cmd,
361 "Reset the board using the FPGA sequencer",
362 "- hard reset to default bank\n"
363 "qixis_reset altbank - reset to alternate bank\n"
364 "qixis_reset nand - reset to nand\n"
365 "qixis_reset sd - reset to sd\n"
366 "qixis_reset sd_qspi - reset to sd with qspi support\n"
367 "qixis_reset qspi - reset to qspi\n"
368 "qixis watchdog <watchdog_period> - set the watchdog period\n"
369 " period: 1s 2s 4s 8s 16s 32s 1min 2min 4min 8min\n"
370 "qixis_reset dump - display the QIXIS registers\n"
371 "qixis_reset emmc - reset to emmc\n"
372 "qixis_reset switch - display switch\n"