1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2011 Freescale Semiconductor
4 * Author: Shengzhou Liu <Shengzhou.Liu@freescale.com>
6 * This file provides support for the QIXIS of some Freescale reference boards.
12 #include <linux/compiler.h>
13 #include <linux/time.h>
17 #ifndef QIXIS_LBMAP_BRDCFG_REG
19 * For consistency with existing platforms
21 #define QIXIS_LBMAP_BRDCFG_REG 0x00
24 #ifdef CONFIG_SYS_I2C_FPGA_ADDR
25 u8 qixis_read_i2c(unsigned int reg)
27 return i2c_reg_read(CONFIG_SYS_I2C_FPGA_ADDR, reg);
30 void qixis_write_i2c(unsigned int reg, u8 value)
33 i2c_reg_write(CONFIG_SYS_I2C_FPGA_ADDR, reg, val);
38 u8 qixis_read(unsigned int reg)
40 void *p = (void *)QIXIS_BASE;
45 void qixis_write(unsigned int reg, u8 value)
47 void *p = (void *)QIXIS_BASE;
49 out_8(p + reg, value);
53 u16 qixis_read_minor(void)
57 /* this data is in little endian */
58 QIXIS_WRITE(tagdata, 5);
59 minor = QIXIS_READ(tagdata);
60 QIXIS_WRITE(tagdata, 6);
61 minor += QIXIS_READ(tagdata) << 8;
66 char *qixis_read_time(char *result)
71 /* timestamp is in 32-bit big endian */
72 for (i = 8; i <= 11; i++) {
73 QIXIS_WRITE(tagdata, i);
74 time = (time << 8) + QIXIS_READ(tagdata);
77 return ctime_r(&time, result);
80 char *qixis_read_tag(char *buf)
85 for (i = 16; i <= 63; i++) {
86 QIXIS_WRITE(tagdata, i);
87 tag = QIXIS_READ(tagdata);
99 * return the string of binary of u8 in the format of
100 * 1010 10_0. The masked bit is filled as underscore.
102 const char *byte_to_binary_mask(u8 val, u8 mask, char *buf)
108 for (i = 0x80; i > 0x08 ; i >>= 1, ptr++)
109 *ptr = (val & i) ? '1' : ((mask & i) ? '_' : '0');
111 for (i = 0x08; i > 0 ; i >>= 1, ptr++)
112 *ptr = (val & i) ? '1' : ((mask & i) ? '_' : '0');
119 #ifdef QIXIS_RST_FORCE_MEM
120 void board_assert_mem_reset(void)
124 rst = QIXIS_READ(rst_frc[0]);
125 if (!(rst & QIXIS_RST_FORCE_MEM))
126 QIXIS_WRITE(rst_frc[0], rst | QIXIS_RST_FORCE_MEM);
129 void board_deassert_mem_reset(void)
133 rst = QIXIS_READ(rst_frc[0]);
134 if (rst & QIXIS_RST_FORCE_MEM)
135 QIXIS_WRITE(rst_frc[0], rst & ~QIXIS_RST_FORCE_MEM);
139 #ifndef CONFIG_SPL_BUILD
140 static void qixis_reset(void)
142 QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET);
145 static void qixis_bank_reset(void)
147 QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
148 QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
151 static void __maybe_unused set_lbmap(int lbmap)
155 reg = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
156 reg = (reg & ~QIXIS_LBMAP_MASK) | lbmap;
157 QIXIS_WRITE(brdcfg[QIXIS_LBMAP_BRDCFG_REG], reg);
160 static void __maybe_unused set_rcw_src(int rcw_src)
164 reg = QIXIS_READ(dutcfg[1]);
165 reg = (reg & ~1) | (rcw_src & 1);
166 QIXIS_WRITE(dutcfg[1], reg);
167 QIXIS_WRITE(dutcfg[0], (rcw_src >> 1) & 0xff);
170 static void qixis_dump_regs(void)
174 printf("id = %02x\n", QIXIS_READ(id));
175 printf("arch = %02x\n", QIXIS_READ(arch));
176 printf("scver = %02x\n", QIXIS_READ(scver));
177 printf("model = %02x\n", QIXIS_READ(model));
178 printf("rst_ctl = %02x\n", QIXIS_READ(rst_ctl));
179 printf("aux = %02x\n", QIXIS_READ(aux));
180 for (i = 0; i < 16; i++)
181 printf("brdcfg%02d = %02x\n", i, QIXIS_READ(brdcfg[i]));
182 for (i = 0; i < 16; i++)
183 printf("dutcfg%02d = %02x\n", i, QIXIS_READ(dutcfg[i]));
184 printf("sclk = %02x%02x%02x\n", QIXIS_READ(sclk[0]),
185 QIXIS_READ(sclk[1]), QIXIS_READ(sclk[2]));
186 printf("dclk = %02x%02x%02x\n", QIXIS_READ(dclk[0]),
187 QIXIS_READ(dclk[1]), QIXIS_READ(dclk[2]));
188 printf("aux = %02x\n", QIXIS_READ(aux));
189 printf("watch = %02x\n", QIXIS_READ(watch));
190 printf("ctl_sys = %02x\n", QIXIS_READ(ctl_sys));
191 printf("rcw_ctl = %02x\n", QIXIS_READ(rcw_ctl));
192 printf("present = %02x\n", QIXIS_READ(present));
193 printf("present2 = %02x\n", QIXIS_READ(present2));
194 printf("clk_spd = %02x\n", QIXIS_READ(clk_spd));
195 printf("stat_dut = %02x\n", QIXIS_READ(stat_dut));
196 printf("stat_sys = %02x\n", QIXIS_READ(stat_sys));
197 printf("stat_alrm = %02x\n", QIXIS_READ(stat_alrm));
200 void __weak qixis_dump_switch(void)
202 puts("Reverse engineering switch is not implemented for this board\n");
205 static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
210 set_lbmap(QIXIS_LBMAP_DFLTBANK);
212 } else if (strcmp(argv[1], "altbank") == 0) {
213 set_lbmap(QIXIS_LBMAP_ALTBANK);
215 } else if (strcmp(argv[1], "nand") == 0) {
216 #ifdef QIXIS_LBMAP_NAND
217 QIXIS_WRITE(rst_ctl, 0x30);
218 QIXIS_WRITE(rcfg_ctl, 0);
219 set_lbmap(QIXIS_LBMAP_NAND);
220 set_rcw_src(QIXIS_RCW_SRC_NAND);
221 QIXIS_WRITE(rcfg_ctl, 0x20);
222 QIXIS_WRITE(rcfg_ctl, 0x21);
224 printf("Not implemented\n");
226 } else if (strcmp(argv[1], "sd") == 0) {
227 #ifdef QIXIS_LBMAP_SD
228 QIXIS_WRITE(rst_ctl, 0x30);
229 QIXIS_WRITE(rcfg_ctl, 0);
230 set_lbmap(QIXIS_LBMAP_SD);
231 set_rcw_src(QIXIS_RCW_SRC_SD);
232 QIXIS_WRITE(rcfg_ctl, 0x20);
233 QIXIS_WRITE(rcfg_ctl, 0x21);
235 printf("Not implemented\n");
237 } else if (strcmp(argv[1], "ifc") == 0) {
238 #ifdef QIXIS_LBMAP_IFC
239 QIXIS_WRITE(rst_ctl, 0x30);
240 QIXIS_WRITE(rcfg_ctl, 0);
241 set_lbmap(QIXIS_LBMAP_IFC);
242 set_rcw_src(QIXIS_RCW_SRC_IFC);
243 QIXIS_WRITE(rcfg_ctl, 0x20);
244 QIXIS_WRITE(rcfg_ctl, 0x21);
246 printf("Not implemented\n");
248 } else if (strcmp(argv[1], "emmc") == 0) {
249 #ifdef QIXIS_LBMAP_EMMC
250 QIXIS_WRITE(rst_ctl, 0x30);
251 QIXIS_WRITE(rcfg_ctl, 0);
252 set_lbmap(QIXIS_LBMAP_EMMC);
253 set_rcw_src(QIXIS_RCW_SRC_EMMC);
254 QIXIS_WRITE(rcfg_ctl, 0x20);
255 QIXIS_WRITE(rcfg_ctl, 0x21);
257 printf("Not implemented\n");
259 } else if (strcmp(argv[1], "sd_qspi") == 0) {
260 #ifdef QIXIS_LBMAP_SD_QSPI
261 QIXIS_WRITE(rst_ctl, 0x30);
262 QIXIS_WRITE(rcfg_ctl, 0);
263 set_lbmap(QIXIS_LBMAP_SD_QSPI);
264 set_rcw_src(QIXIS_RCW_SRC_SD);
265 qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x20);
266 qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x21);
268 printf("Not implemented\n");
270 } else if (strcmp(argv[1], "qspi") == 0) {
271 #ifdef QIXIS_LBMAP_QSPI
272 QIXIS_WRITE(rst_ctl, 0x30);
273 QIXIS_WRITE(rcfg_ctl, 0);
274 set_lbmap(QIXIS_LBMAP_QSPI);
275 set_rcw_src(QIXIS_RCW_SRC_QSPI);
276 qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x20);
277 qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x21);
279 printf("Not implemented\n");
281 } else if (strcmp(argv[1], "watchdog") == 0) {
282 static char *period[9] = {"2s", "4s", "8s", "16s", "32s",
283 "1min", "2min", "4min", "8min"};
284 u8 rcfg = QIXIS_READ(rcfg_ctl);
286 if (argv[2] == NULL) {
287 printf("qixis watchdog <watchdog_period>\n");
290 for (i = 0; i < ARRAY_SIZE(period); i++) {
291 if (strcmp(argv[2], period[i]) == 0) {
292 /* disable watchdog */
293 QIXIS_WRITE(rcfg_ctl,
294 rcfg & ~QIXIS_RCFG_CTL_WATCHDOG_ENBLE);
295 QIXIS_WRITE(watch, ((i<<2) - 1));
296 QIXIS_WRITE(rcfg_ctl, rcfg);
300 } else if (strcmp(argv[1], "dump") == 0) {
303 } else if (strcmp(argv[1], "switch") == 0) {
307 printf("Invalid option: %s\n", argv[1]);
315 qixis_reset, CONFIG_SYS_MAXARGS, 1, qixis_reset_cmd,
316 "Reset the board using the FPGA sequencer",
317 "- hard reset to default bank\n"
318 "qixis_reset altbank - reset to alternate bank\n"
319 "qixis_reset nand - reset to nand\n"
320 "qixis_reset sd - reset to sd\n"
321 "qixis_reset sd_qspi - reset to sd with qspi support\n"
322 "qixis_reset qspi - reset to qspi\n"
323 "qixis watchdog <watchdog_period> - set the watchdog period\n"
324 " period: 1s 2s 4s 8s 16s 32s 1min 2min 4min 8min\n"
325 "qixis_reset dump - display the QIXIS registers\n"
326 "qixis_reset switch - display switch\n"