2 * Copyright 2014 Freescale Semiconductor, Inc.
3 * Authors: Priyanka Jain <Priyanka.Jain@freescale.com>
4 * Wang Dongsheng <dongsheng.wang@freescale.com>
6 * This file is copied and modified from the original t1040qds/diu.c.
7 * Encoder can be used in T104x and LSx Platform.
9 * SPDX-License-Identifier: GPL-2.0+
13 #include <stdio_dev.h>
16 #define I2C_DVI_INPUT_DATA_FORMAT_REG 0x1F
17 #define I2C_DVI_PLL_CHARGE_CNTL_REG 0x33
18 #define I2C_DVI_PLL_DIVIDER_REG 0x34
19 #define I2C_DVI_PLL_SUPPLY_CNTL_REG 0x35
20 #define I2C_DVI_PLL_FILTER_REG 0x36
21 #define I2C_DVI_TEST_PATTERN_REG 0x48
22 #define I2C_DVI_POWER_MGMT_REG 0x49
23 #define I2C_DVI_LOCK_STATE_REG 0x4D
24 #define I2C_DVI_SYNC_POLARITY_REG 0x56
27 * Set VSYNC/HSYNC to active high. This is polarity of sync signals
28 * from DIU->DVI. The DIU default is active igh, so DVI is set to
31 #define I2C_DVI_INPUT_DATA_FORMAT_VAL 0x98
33 #define I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL 0x06
34 #define I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL 0x26
35 #define I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL 0xA0
36 #define I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL 0x08
37 #define I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL 0x16
38 #define I2C_DVI_PLL_FILTER_LOW_SPEED_VAL 0x60
40 /* Clear test pattern */
41 #define I2C_DVI_TEST_PATTERN_VAL 0x18
42 /* Exit Power-down mode */
43 #define I2C_DVI_POWER_MGMT_VAL 0xC0
45 /* Monitor polarity is handled via DVI Sync Polarity Register */
46 #define I2C_DVI_SYNC_POLARITY_VAL 0x00
48 /* Programming of HDMI Chrontel CH7301 connector */
49 int diu_set_dvi_encoder(unsigned int pixclock)
54 temp = I2C_DVI_TEST_PATTERN_VAL;
55 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_TEST_PATTERN_REG, 1,
58 puts("I2C: failed to select proper dvi test pattern\n");
61 temp = I2C_DVI_INPUT_DATA_FORMAT_VAL;
62 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_INPUT_DATA_FORMAT_REG,
65 puts("I2C: failed to select dvi input data format\n");
69 /* Set Sync polarity register */
70 temp = I2C_DVI_SYNC_POLARITY_VAL;
71 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_SYNC_POLARITY_REG, 1,
74 puts("I2C: failed to select dvi syc polarity\n");
78 /* Set PLL registers based on pixel clock rate*/
79 if (pixclock > 65000000) {
80 temp = I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL;
81 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
82 I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1);
84 puts("I2C: failed to select dvi pll charge_cntl\n");
87 temp = I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL;
88 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
89 I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1);
91 puts("I2C: failed to select dvi pll divider\n");
94 temp = I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL;
95 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
96 I2C_DVI_PLL_FILTER_REG, 1, &temp, 1);
98 puts("I2C: failed to select dvi pll filter\n");
102 temp = I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL;
103 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
104 I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1);
106 puts("I2C: failed to select dvi pll charge_cntl\n");
109 temp = I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL;
110 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
111 I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1);
113 puts("I2C: failed to select dvi pll divider\n");
116 temp = I2C_DVI_PLL_FILTER_LOW_SPEED_VAL;
117 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
118 I2C_DVI_PLL_FILTER_REG, 1, &temp, 1);
120 puts("I2C: failed to select dvi pll filter\n");
125 temp = I2C_DVI_POWER_MGMT_VAL;
126 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_POWER_MGMT_REG, 1,
129 puts("I2C: failed to select dvi power mgmt\n");