1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2014 Freescale Semiconductor, Inc.
5 * Authors: Priyanka Jain <Priyanka.Jain@freescale.com>
6 * Wang Dongsheng <dongsheng.wang@freescale.com>
8 * This file is copied and modified from the original t1040qds/diu.c.
9 * Encoder can be used in T104x and LSx Platform.
13 #include <stdio_dev.h>
16 #define I2C_DVI_INPUT_DATA_FORMAT_REG 0x1F
17 #define I2C_DVI_PLL_CHARGE_CNTL_REG 0x33
18 #define I2C_DVI_PLL_DIVIDER_REG 0x34
19 #define I2C_DVI_PLL_SUPPLY_CNTL_REG 0x35
20 #define I2C_DVI_PLL_FILTER_REG 0x36
21 #define I2C_DVI_TEST_PATTERN_REG 0x48
22 #define I2C_DVI_POWER_MGMT_REG 0x49
23 #define I2C_DVI_LOCK_STATE_REG 0x4D
24 #define I2C_DVI_SYNC_POLARITY_REG 0x56
27 * Set VSYNC/HSYNC to active high. This is polarity of sync signals
28 * from DIU->DVI. The DIU default is active igh, so DVI is set to
31 #define I2C_DVI_INPUT_DATA_FORMAT_VAL 0x98
33 #define I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL 0x06
34 #define I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL 0x26
35 #define I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL 0xA0
36 #define I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL 0x08
37 #define I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL 0x16
38 #define I2C_DVI_PLL_FILTER_LOW_SPEED_VAL 0x60
40 /* Clear test pattern */
41 #define I2C_DVI_TEST_PATTERN_VAL 0x18
42 /* Exit Power-down mode */
43 #define I2C_DVI_POWER_MGMT_VAL 0xC0
45 /* Monitor polarity is handled via DVI Sync Polarity Register */
46 #define I2C_DVI_SYNC_POLARITY_VAL 0x00
48 /* Programming of HDMI Chrontel CH7301 connector */
49 int diu_set_dvi_encoder(unsigned int pixclock)
54 temp = I2C_DVI_TEST_PATTERN_VAL;
58 ret = i2c_get_chip_for_busnum(CONFIG_SYS_I2C_DVI_BUS_NUM,
59 CONFIG_SYS_I2C_DVI_ADDR,
62 printf("%s: Cannot find udev for a bus %d\n", __func__,
63 CONFIG_SYS_I2C_DVI_BUS_NUM);
66 ret = dm_i2c_write(dev, I2C_DVI_TEST_PATTERN_REG, &temp, 1);
68 puts("I2C: failed to select proper dvi test pattern\n");
71 temp = I2C_DVI_INPUT_DATA_FORMAT_VAL;
72 ret = dm_i2c_write(dev, I2C_DVI_INPUT_DATA_FORMAT_REG, &temp, 1);
74 puts("I2C: failed to select dvi input data format\n");
78 /* Set Sync polarity register */
79 temp = I2C_DVI_SYNC_POLARITY_VAL;
80 ret = dm_i2c_write(dev, I2C_DVI_SYNC_POLARITY_REG, &temp, 1);
82 puts("I2C: failed to select dvi syc polarity\n");
86 /* Set PLL registers based on pixel clock rate*/
87 if (pixclock > 65000000) {
88 temp = I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL;
89 ret = dm_i2c_write(dev, I2C_DVI_PLL_CHARGE_CNTL_REG, &temp, 1);
91 puts("I2C: failed to select dvi pll charge_cntl\n");
94 temp = I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL;
95 ret = dm_i2c_write(dev, I2C_DVI_PLL_DIVIDER_REG, &temp, 1);
97 puts("I2C: failed to select dvi pll divider\n");
100 temp = I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL;
101 ret = dm_i2c_write(dev, I2C_DVI_PLL_FILTER_REG, &temp, 1);
103 puts("I2C: failed to select dvi pll filter\n");
107 temp = I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL;
108 ret = dm_i2c_write(dev, I2C_DVI_PLL_CHARGE_CNTL_REG, &temp, 1);
110 puts("I2C: failed to select dvi pll charge_cntl\n");
113 temp = I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL;
114 ret = dm_i2c_write(dev, I2C_DVI_PLL_DIVIDER_REG, &temp, 1);
116 puts("I2C: failed to select dvi pll divider\n");
119 temp = I2C_DVI_PLL_FILTER_LOW_SPEED_VAL;
120 ret = dm_i2c_write(dev, I2C_DVI_PLL_FILTER_REG, &temp, 1);
122 puts("I2C: failed to select dvi pll filter\n");
127 temp = I2C_DVI_POWER_MGMT_VAL;
128 ret = dm_i2c_write(dev, I2C_DVI_POWER_MGMT_REG, &temp, 1);
130 puts("I2C: failed to select dvi power mgmt\n");
134 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_TEST_PATTERN_REG, 1,
137 puts("I2C: failed to select proper dvi test pattern\n");
140 temp = I2C_DVI_INPUT_DATA_FORMAT_VAL;
141 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_INPUT_DATA_FORMAT_REG,
144 puts("I2C: failed to select dvi input data format\n");
148 /* Set Sync polarity register */
149 temp = I2C_DVI_SYNC_POLARITY_VAL;
150 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_SYNC_POLARITY_REG, 1,
153 puts("I2C: failed to select dvi syc polarity\n");
157 /* Set PLL registers based on pixel clock rate*/
158 if (pixclock > 65000000) {
159 temp = I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL;
160 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
161 I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1);
163 puts("I2C: failed to select dvi pll charge_cntl\n");
166 temp = I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL;
167 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
168 I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1);
170 puts("I2C: failed to select dvi pll divider\n");
173 temp = I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL;
174 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
175 I2C_DVI_PLL_FILTER_REG, 1, &temp, 1);
177 puts("I2C: failed to select dvi pll filter\n");
181 temp = I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL;
182 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
183 I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1);
185 puts("I2C: failed to select dvi pll charge_cntl\n");
188 temp = I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL;
189 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
190 I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1);
192 puts("I2C: failed to select dvi pll divider\n");
195 temp = I2C_DVI_PLL_FILTER_LOW_SPEED_VAL;
196 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
197 I2C_DVI_PLL_FILTER_REG, 1, &temp, 1);
199 puts("I2C: failed to select dvi pll filter\n");
204 temp = I2C_DVI_POWER_MGMT_VAL;
205 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_POWER_MGMT_REG, 1,
208 puts("I2C: failed to select dvi power mgmt\n");