1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2014 Freescale Semiconductor, Inc.
5 * Authors: Priyanka Jain <Priyanka.Jain@freescale.com>
6 * Wang Dongsheng <dongsheng.wang@freescale.com>
8 * This file is copied and modified from the original t1040qds/diu.c.
9 * Encoder can be used in T104x and LSx Platform.
13 #include <stdio_dev.h>
15 #include <linux/delay.h>
17 #define I2C_DVI_INPUT_DATA_FORMAT_REG 0x1F
18 #define I2C_DVI_PLL_CHARGE_CNTL_REG 0x33
19 #define I2C_DVI_PLL_DIVIDER_REG 0x34
20 #define I2C_DVI_PLL_SUPPLY_CNTL_REG 0x35
21 #define I2C_DVI_PLL_FILTER_REG 0x36
22 #define I2C_DVI_TEST_PATTERN_REG 0x48
23 #define I2C_DVI_POWER_MGMT_REG 0x49
24 #define I2C_DVI_LOCK_STATE_REG 0x4D
25 #define I2C_DVI_SYNC_POLARITY_REG 0x56
28 * Set VSYNC/HSYNC to active high. This is polarity of sync signals
29 * from DIU->DVI. The DIU default is active igh, so DVI is set to
32 #define I2C_DVI_INPUT_DATA_FORMAT_VAL 0x98
34 #define I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL 0x06
35 #define I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL 0x26
36 #define I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL 0xA0
37 #define I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL 0x08
38 #define I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL 0x16
39 #define I2C_DVI_PLL_FILTER_LOW_SPEED_VAL 0x60
41 /* Clear test pattern */
42 #define I2C_DVI_TEST_PATTERN_VAL 0x18
43 /* Exit Power-down mode */
44 #define I2C_DVI_POWER_MGMT_VAL 0xC0
46 /* Monitor polarity is handled via DVI Sync Polarity Register */
47 #define I2C_DVI_SYNC_POLARITY_VAL 0x00
49 /* Programming of HDMI Chrontel CH7301 connector */
50 int diu_set_dvi_encoder(unsigned int pixclock)
55 temp = I2C_DVI_TEST_PATTERN_VAL;
59 ret = i2c_get_chip_for_busnum(CONFIG_SYS_I2C_DVI_BUS_NUM,
60 CONFIG_SYS_I2C_DVI_ADDR,
63 printf("%s: Cannot find udev for a bus %d\n", __func__,
64 CONFIG_SYS_I2C_DVI_BUS_NUM);
67 ret = dm_i2c_write(dev, I2C_DVI_TEST_PATTERN_REG, &temp, 1);
69 puts("I2C: failed to select proper dvi test pattern\n");
72 temp = I2C_DVI_INPUT_DATA_FORMAT_VAL;
73 ret = dm_i2c_write(dev, I2C_DVI_INPUT_DATA_FORMAT_REG, &temp, 1);
75 puts("I2C: failed to select dvi input data format\n");
79 /* Set Sync polarity register */
80 temp = I2C_DVI_SYNC_POLARITY_VAL;
81 ret = dm_i2c_write(dev, I2C_DVI_SYNC_POLARITY_REG, &temp, 1);
83 puts("I2C: failed to select dvi syc polarity\n");
87 /* Set PLL registers based on pixel clock rate*/
88 if (pixclock > 65000000) {
89 temp = I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL;
90 ret = dm_i2c_write(dev, I2C_DVI_PLL_CHARGE_CNTL_REG, &temp, 1);
92 puts("I2C: failed to select dvi pll charge_cntl\n");
95 temp = I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL;
96 ret = dm_i2c_write(dev, I2C_DVI_PLL_DIVIDER_REG, &temp, 1);
98 puts("I2C: failed to select dvi pll divider\n");
101 temp = I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL;
102 ret = dm_i2c_write(dev, I2C_DVI_PLL_FILTER_REG, &temp, 1);
104 puts("I2C: failed to select dvi pll filter\n");
108 temp = I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL;
109 ret = dm_i2c_write(dev, I2C_DVI_PLL_CHARGE_CNTL_REG, &temp, 1);
111 puts("I2C: failed to select dvi pll charge_cntl\n");
114 temp = I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL;
115 ret = dm_i2c_write(dev, I2C_DVI_PLL_DIVIDER_REG, &temp, 1);
117 puts("I2C: failed to select dvi pll divider\n");
120 temp = I2C_DVI_PLL_FILTER_LOW_SPEED_VAL;
121 ret = dm_i2c_write(dev, I2C_DVI_PLL_FILTER_REG, &temp, 1);
123 puts("I2C: failed to select dvi pll filter\n");
128 temp = I2C_DVI_POWER_MGMT_VAL;
129 ret = dm_i2c_write(dev, I2C_DVI_POWER_MGMT_REG, &temp, 1);
131 puts("I2C: failed to select dvi power mgmt\n");
135 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_TEST_PATTERN_REG, 1,
138 puts("I2C: failed to select proper dvi test pattern\n");
141 temp = I2C_DVI_INPUT_DATA_FORMAT_VAL;
142 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_INPUT_DATA_FORMAT_REG,
145 puts("I2C: failed to select dvi input data format\n");
149 /* Set Sync polarity register */
150 temp = I2C_DVI_SYNC_POLARITY_VAL;
151 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_SYNC_POLARITY_REG, 1,
154 puts("I2C: failed to select dvi syc polarity\n");
158 /* Set PLL registers based on pixel clock rate*/
159 if (pixclock > 65000000) {
160 temp = I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL;
161 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
162 I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1);
164 puts("I2C: failed to select dvi pll charge_cntl\n");
167 temp = I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL;
168 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
169 I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1);
171 puts("I2C: failed to select dvi pll divider\n");
174 temp = I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL;
175 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
176 I2C_DVI_PLL_FILTER_REG, 1, &temp, 1);
178 puts("I2C: failed to select dvi pll filter\n");
182 temp = I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL;
183 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
184 I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1);
186 puts("I2C: failed to select dvi pll charge_cntl\n");
189 temp = I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL;
190 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
191 I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1);
193 puts("I2C: failed to select dvi pll divider\n");
196 temp = I2C_DVI_PLL_FILTER_LOW_SPEED_VAL;
197 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
198 I2C_DVI_PLL_FILTER_REG, 1, &temp, 1);
200 puts("I2C: failed to select dvi pll filter\n");
205 temp = I2C_DVI_POWER_MGMT_VAL;
206 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_POWER_MGMT_REG, 1,
209 puts("I2C: failed to select dvi power mgmt\n");