board/freescale/common/cds_via.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2006 Freescale Semiconductor.
   4  */
   5
   6 #include <common.h>
   7 #include <pci.h>
   8
   9 /* Config the VIA chip */
  10 void mpc85xx_config_via(struct pci_controller *hose,
  11                         pci_dev_t dev, struct pci_config_table *tab)
  12 {
  13         pci_dev_t bridge;
  14         unsigned int cmdstat;
  15
  16         /* Enable USB and IDE functions */
  17         pci_hose_write_config_byte(hose, dev, 0x48, 0x08);
  18
  19         pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
  20         cmdstat |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY| PCI_COMMAND_MASTER;
  21         pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
  22         pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
  23         pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
  24
  25         /*
  26          * Force the backplane P2P bridge to have a window
  27          * open from 0x00000000-0x00001fff in PCI I/O space.
  28          * This allows legacy I/O (i8259, etc) on the VIA
  29          * southbridge to be accessed.
  30          */
  31 #ifdef CONFIG_TARGET_MPC8548CDS_LEGACY
  32         bridge = PCI_BDF(0, 17, 0);
  33 #else
  34         bridge = PCI_BDF(0, 28, 0);
  35 #endif
  36         pci_hose_write_config_byte(hose, bridge, PCI_IO_BASE, 0);
  37         pci_hose_write_config_word(hose, bridge, PCI_IO_BASE_UPPER16, 0);
  38         pci_hose_write_config_byte(hose, bridge, PCI_IO_LIMIT, 0x10);
  39         pci_hose_write_config_word(hose, bridge, PCI_IO_LIMIT_UPPER16, 0);
  40 }
  41
  42 /* Function 1, IDE */
  43 void mpc85xx_config_via_usbide(struct pci_controller *hose,
  44                                pci_dev_t dev, struct pci_config_table *tab)
  45 {
  46         pciauto_config_device(hose, dev);
  47         /*
  48          * Since the P2P window was forced to cover the fixed
  49          * legacy I/O addresses, it is necessary to manually
  50          * place the base addresses for the IDE and USB functions
  51          * within this window.
  52          */
  53         pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1ff8);
  54         pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1ff4);
  55         pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1fe8);
  56         pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_3, 0x1fe4);
  57         pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fd0);
  58 }
  59
  60 /* Function 2, USB ports 0-1 */
  61 void mpc85xx_config_via_usb(struct pci_controller *hose,
  62                             pci_dev_t dev, struct pci_config_table *tab)
  63 {
  64         pciauto_config_device(hose, dev);
  65
  66         pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fa0);
  67 }
  68
  69 /* Function 3, USB ports 2-3 */
  70 void mpc85xx_config_via_usb2(struct pci_controller *hose,
  71                              pci_dev_t dev, struct pci_config_table *tab)
  72 {
  73         pciauto_config_device(hose, dev);
  74
  75         pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1f80);
  76 }
  77
  78 /* Function 5, Power Management */
  79 void mpc85xx_config_via_power(struct pci_controller *hose,
  80                               pci_dev_t dev, struct pci_config_table *tab)
  81 {
  82         pciauto_config_device(hose, dev);
  83
  84         pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1e00);
  85         pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1dfc);
  86         pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1df8);
  87 }
  88
  89 /* Function 6, AC97 Interface */
  90 void mpc85xx_config_via_ac97(struct pci_controller *hose,
  91                              pci_dev_t dev, struct pci_config_table *tab)
  92 {
  93         pciauto_config_device(hose, dev);
  94
  95         pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1c00);
  96 }