1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2013 Freescale Semiconductor, Inc.
9 struct fsl_e_tlb_entry tlb_table[] = {
10 /* TLB 0 - for temp stack in cache */
11 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
12 MAS3_SX|MAS3_SW|MAS3_SR, 0,
13 0, 0, BOOKE_PAGESZ_4K, 0),
14 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
15 CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
16 MAS3_SX|MAS3_SW|MAS3_SR, 0,
17 0, 0, BOOKE_PAGESZ_4K, 0),
18 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
19 CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
20 MAS3_SX|MAS3_SW|MAS3_SR, 0,
21 0, 0, BOOKE_PAGESZ_4K, 0),
22 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
23 CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
24 MAS3_SX|MAS3_SW|MAS3_SR, 0,
25 0, 0, BOOKE_PAGESZ_4K, 0),
28 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
29 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
30 0, 0, BOOKE_PAGESZ_1M, 1),
32 #ifndef CONFIG_SPL_BUILD
33 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
34 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
35 0, 1, BOOKE_PAGESZ_64M, 1),
38 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
39 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
40 0, 2, BOOKE_PAGESZ_256M, 1),
42 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
43 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
44 0, 3, BOOKE_PAGESZ_256K, 1),
48 SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
49 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
50 0, 4, BOOKE_PAGESZ_64K, 1),
52 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
53 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
54 0, 5, BOOKE_PAGESZ_64K, 1),
56 SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE,
57 CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS,
58 MAS3_SX|MAS3_SW|MAS3_SR, 0,
59 0, 6, BOOKE_PAGESZ_256K, 1),
60 SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE + 0x40000,
61 CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS + 0x40000,
62 MAS3_SX|MAS3_SW|MAS3_SR, 0,
63 0, 7, BOOKE_PAGESZ_256K, 1),
65 #if defined(CONFIG_SYS_RAMBOOT) || \
66 (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
67 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
68 CONFIG_SYS_DDR_SDRAM_BASE,
69 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
70 0, 8, BOOKE_PAGESZ_256M, 1),
71 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
72 CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
73 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
74 0, 9, BOOKE_PAGESZ_256M, 1),
77 #ifdef CONFIG_SYS_INIT_L2_ADDR
78 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
79 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
80 0, 12, BOOKE_PAGESZ_256K, 1)
84 int num_tlb_entries = ARRAY_SIZE(tlb_table);