board/freescale/c29xpcie/ddr.c

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the Free
   6  * Software Foundation; either version 2 of the License, or (at your option)
   7  * any later version.
   8  */
   9
  10 #include <common.h>
  11 #include <asm/fsl_law.h>
  12 #include <asm/fsl_ddr_sdram.h>
  13 #include <asm/fsl_ddr_dimm_params.h>
  14
  15 /*
  16  * Micron MT41J128M16HA-15E
  17  * */
  18 dimm_params_t ddr_raw_timing = {
  19         .n_ranks = 1,
  20         .rank_density = 536870912u,
  21         .capacity = 536870912u,
  22         .primary_sdram_width = 32,
  23         .ec_sdram_width = 8,
  24         .registered_dimm = 0,
  25         .mirrored_dimm = 0,
  26         .n_row_addr = 14,
  27         .n_col_addr = 10,
  28         .n_banks_per_sdram_device = 8,
  29         .edc_config = 2,
  30         .burst_lengths_bitmask = 0x0c,
  31
  32         .tCKmin_X_ps = 1650,
  33         .caslat_X = 0x7e << 4,  /* 5,6,7,8,9,10 */
  34         .tAA_ps = 14050,
  35         .tWR_ps = 15000,
  36         .tRCD_ps = 13500,
  37         .tRRD_ps = 75000,
  38         .tRP_ps = 13500,
  39         .tRAS_ps = 40000,
  40         .tRC_ps = 49500,
  41         .tRFC_ps = 160000,
  42         .tWTR_ps = 75000,
  43         .tRTP_ps = 75000,
  44         .refresh_rate_ps = 7800000,
  45         .tFAW_ps = 30000,
  46 };
  47
  48 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
  49                 unsigned int controller_number,
  50                 unsigned int dimm_number)
  51 {
  52         const char dimm_model[] = "Fixed DDR on board";
  53
  54         if ((controller_number == 0) && (dimm_number == 0)) {
  55                 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
  56                 memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
  57                 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
  58         }
  59
  60         return 0;
  61 }
  62
  63 void fsl_ddr_board_options(memctl_options_t *popts,
  64                                 dimm_params_t *pdimm,
  65                                 unsigned int ctrl_num)
  66 {
  67         int i;
  68         popts->clk_adjust = 2;
  69         popts->cpo_override = 0x1f;
  70         popts->write_data_delay = 4;
  71         popts->half_strength_driver_enable = 1;
  72         popts->bstopre = 0x3cf;
  73         popts->quad_rank_present = 1;
  74         popts->rtt_override = 1;
  75         popts->rtt_override_value = 1;
  76         popts->dynamic_power = 1;
  77         /* Write leveling override */
  78         popts->wrlvl_en = 1;
  79         popts->wrlvl_override = 1;
  80         popts->wrlvl_sample = 0xf;
  81         popts->wrlvl_start = 0x4;
  82         popts->trwt_override = 1;
  83         popts->trwt = 0;
  84
  85         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  86                 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
  87                 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
  88         }
  89 }