1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2013 Freescale Semiconductor, Inc.
10 #include <asm/processor.h>
12 #include <asm/cache.h>
13 #include <asm/immap_85xx.h>
17 #include <linux/libfdt.h>
18 #include <fdt_support.h>
26 #include <fsl_ddr_sdram.h>
27 #include <jffs2/load_kernel.h>
33 #include <asm/fsl_pci.h>
36 #include "../common/qixis.h"
37 DECLARE_GLOBAL_DATA_PTR;
40 int board_early_init_f(void)
42 struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
44 setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
49 void board_config_serdes_mux(void)
51 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
52 u32 pordevsr = in_be32(&gur->pordevsr);
53 u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
54 MPC85xx_PORDEVSR_IO_SEL_SHIFT;
57 /* PEX(1) PEX(2) CPRI 2 CPRI 1 */
68 QIXIS_WRITE_I2C(brdcfg[4], 0x03);
71 /* PEX(1) PEX(2) SGMII1 CPRI 1 */
82 QIXIS_WRITE_I2C(brdcfg[4], 0x01);
85 /* PEX(1) PEX(2) SGMII1 SGMII2 */
88 QIXIS_WRITE_I2C(brdcfg[4], 0x00);
91 /* PEX(1) SGMII2 CPRI 2 CPRI 1 */
102 QIXIS_WRITE_I2C(brdcfg[4], 0x07);
105 /* PEX(1) SGMII2 SGMII1 CPRI 1 */
116 QIXIS_WRITE_I2C(brdcfg[4], 0x05);
119 /* SGMII1 SGMII2 CPRI 2 CPRI 1 */
125 QIXIS_WRITE_I2C(brdcfg[4], 0x0F);
134 /* Configure DSP DDR controller */
135 void dsp_ddr_configure(void)
138 *There are separate DDR-controllers for DSP and PowerPC side DDR.
139 *copy the ddr controller settings from PowerPC side DDR controller
140 *to the DSP DDR controller as connected DDR memories are similar.
142 struct ccsr_ddr __iomem *pa_ddr =
143 (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
144 struct ccsr_ddr temp_ddr;
145 struct ccsr_ddr __iomem *dsp_ddr =
146 (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR;
148 memcpy(&temp_ddr, pa_ddr, sizeof(struct ccsr_ddr));
149 temp_ddr.cs0_bnds = CONFIG_SYS_DDR1_CS0_BNDS;
150 temp_ddr.sdram_cfg &= ~SDRAM_CFG_MEM_EN;
151 memcpy(dsp_ddr, &temp_ddr, sizeof(struct ccsr_ddr));
152 dsp_ddr->sdram_cfg |= SDRAM_CFG_MEM_EN;
155 int board_early_init_r(void)
157 #ifdef CONFIG_MTD_NOR_FLASH
158 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
159 int flash_esel = find_tlb_idx((void *)flashbase, 1);
162 * Remap Boot flash region to caching-inhibited
163 * so that flash can be erased properly.
166 /* Flush d-cache and invalidate i-cache of any FLASH data */
170 if (flash_esel == -1) {
171 /* very unlikely unless something is messed up */
172 puts("Error: Could not find TLB for FLASH BASE\n");
173 flash_esel = 2; /* give our best effort to continue */
175 /* invalidate existing TLB entry for flash */
176 disable_tlb(flash_esel);
179 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
180 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
181 0, flash_esel, BOOKE_PAGESZ_64M, 1);
183 set_tlb(1, flashbase + 0x4000000,
184 CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000,
185 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
186 0, flash_esel+1, BOOKE_PAGESZ_64M, 1);
188 board_config_serdes_mux();
194 void pci_init_board(void)
196 fsl_pcie_init_board(0);
198 #endif /* ifdef CONFIG_PCI */
202 struct cpu_type *cpu;
206 printf("Board: %sQDS\n", cpu->name);
208 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x,\n",
209 QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver));
211 sw = QIXIS_READ(brdcfg[0]);
212 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
214 printf("IFC chip select:");
226 printf("Invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
233 int board_eth_init(bd_t *bis)
235 #ifdef CONFIG_TSEC_ENET
236 struct fsl_pq_mdio_info mdio_info;
237 struct tsec_info_struct tsec_info[4];
241 SET_STD_TSEC_INFO(tsec_info[num], 1);
247 SET_STD_TSEC_INFO(tsec_info[num], 2);
251 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
252 mdio_info.name = DEFAULT_MII_NAME;
254 fsl_pq_mdio_init(bis, &mdio_info);
255 tsec_eth_init(bis, tsec_info, num);
265 #define USBMUX_SEL_MASK 0xc0
266 #define USBMUX_SEL_UART2 0xc0
267 #define USBMUX_SEL_USB 0x40
268 #define SPIMUX_SEL_UART3 0x80
269 #define GPS_MUX_SEL_GPS 0x40
271 #define TSEC_1588_CLKIN_MASK 0x03
272 #define CON_XCVR_REF_CLK 0x00
274 int misc_init_r(void)
277 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
278 u32 porbmsr = in_be32(&gur->porbmsr);
279 u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
281 /*Configure 1588 clock-in source from RF Card*/
282 val = QIXIS_READ_I2C(brdcfg[5]);
283 QIXIS_WRITE_I2C(brdcfg[5],
284 (val & ~(TSEC_1588_CLKIN_MASK)) | CON_XCVR_REF_CLK);
286 if (hwconfig("uart2") && hwconfig("usb1")) {
287 printf("UART2 and USB cannot work together on the board\n");
288 printf("Remove one from hwconfig and reset\n");
290 if (hwconfig("uart2")) {
291 val = QIXIS_READ_I2C(brdcfg[5]);
292 QIXIS_WRITE_I2C(brdcfg[5],
293 (val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_UART2);
294 clrbits_be32(&gur->pmuxcr3,
295 MPC85xx_PMUXCR3_USB_SEL_MASK);
296 setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART2_SEL);
298 /* By default USB should be selected.
299 * Programming FPGA to select USB. */
300 val = QIXIS_READ_I2C(brdcfg[5]);
301 QIXIS_WRITE_I2C(brdcfg[5],
302 (val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_USB);
307 if (hwconfig("sim")) {
308 if (romloc == PORBMSR_ROMLOC_NAND_2K ||
309 romloc == PORBMSR_ROMLOC_NOR ||
310 romloc == PORBMSR_ROMLOC_SPI) {
312 val = QIXIS_READ_I2C(brdcfg[3]);
313 QIXIS_WRITE_I2C(brdcfg[3], val|0x10);
314 clrbits_be32(&gur->pmuxcr,
315 MPC85xx_PMUXCR0_SIM_SEL_MASK);
316 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR0_SIM_SEL);
320 if (hwconfig("uart3")) {
321 if (romloc == PORBMSR_ROMLOC_NAND_2K ||
322 romloc == PORBMSR_ROMLOC_NOR ||
323 romloc == PORBMSR_ROMLOC_SDHC) {
325 /* UART3 and SPI1 (Flashes) are muxed together */
326 val = QIXIS_READ_I2C(brdcfg[3]);
327 QIXIS_WRITE_I2C(brdcfg[3], (val | SPIMUX_SEL_UART3));
328 clrbits_be32(&gur->pmuxcr3,
329 MPC85xx_PMUXCR3_UART3_SEL_MASK);
330 setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART3_SEL);
332 /* MUX to select UART3 connection to J24 header
334 val = QIXIS_READ_I2C(brdcfg[6]);
336 QIXIS_WRITE_I2C(brdcfg[6],
337 (val | GPS_MUX_SEL_GPS));
339 QIXIS_WRITE_I2C(brdcfg[6],
340 (val & ~(GPS_MUX_SEL_GPS)));
346 void fdt_del_node_compat(void *blob, const char *compatible)
349 int off = fdt_node_offset_by_compatible(blob, -1, compatible);
351 printf("WARNING: could not find compatible node %s: %s.\n",
352 compatible, fdt_strerror(off));
355 err = fdt_del_node(blob, off);
357 printf("WARNING: could not remove %s: %s.\n",
358 compatible, fdt_strerror(err));
362 #if defined(CONFIG_OF_BOARD_SETUP)
363 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
364 static const struct node_info nodes[] = {
365 { "cfi-flash", MTD_DEV_TYPE_NOR, },
366 { "fsl,ifc-nand", MTD_DEV_TYPE_NAND, },
369 int ft_board_setup(void *blob, bd_t *bd)
374 ft_cpu_setup(blob, bd);
376 base = env_get_bootm_low();
377 size = env_get_bootm_size();
379 #if defined(CONFIG_PCI)
383 fdt_fixup_memory(blob, (u64)base, (u64)size);
384 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
385 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
388 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
389 u32 porbmsr = in_be32(&gur->porbmsr);
390 u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
392 if (!(hwconfig("uart2") && hwconfig("usb1"))) {
393 /* If uart2 is there in hwconfig remove usb node from
396 if (hwconfig("uart2")) {
397 /* remove dts usb node */
398 fdt_del_node_compat(blob, "fsl-usb2-dr");
400 fsl_fdt_fixup_dr_usb(blob, bd);
401 fdt_del_node_and_alias(blob, "serial2");
405 if (hwconfig("uart3")) {
406 if (romloc == PORBMSR_ROMLOC_NAND_2K ||
407 romloc == PORBMSR_ROMLOC_NOR ||
408 romloc == PORBMSR_ROMLOC_SDHC)
409 /* Delete SPI node from the device tree */
410 fdt_del_node_and_alias(blob, "spi1");
412 fdt_del_node_and_alias(blob, "serial3");
414 if (hwconfig("sim")) {
415 if (romloc == PORBMSR_ROMLOC_NAND_2K ||
416 romloc == PORBMSR_ROMLOC_NOR ||
417 romloc == PORBMSR_ROMLOC_SPI) {
419 /* remove dts sdhc node */
420 fdt_del_node_compat(blob, "fsl,esdhc");
421 } else if (romloc == PORBMSR_ROMLOC_SDHC) {
423 /* remove dts sim node */
424 fdt_del_node_compat(blob, "fsl,sim-v1.0");
425 printf("SIM & SDHC can't work together on the board");
426 printf("\nRemove sim from hwconfig and reset\n");