1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2013 Freescale Semiconductor, Inc.
9 #include <asm/processor.h>
11 #include <asm/cache.h>
12 #include <asm/immap_85xx.h>
16 #include <linux/libfdt.h>
17 #include <fdt_support.h>
25 #include <fsl_ddr_sdram.h>
26 #include <jffs2/load_kernel.h>
32 #include <asm/fsl_pci.h>
35 #include "../common/qixis.h"
36 DECLARE_GLOBAL_DATA_PTR;
39 int board_early_init_f(void)
41 struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
43 setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
48 void board_config_serdes_mux(void)
50 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
51 u32 pordevsr = in_be32(&gur->pordevsr);
52 u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
53 MPC85xx_PORDEVSR_IO_SEL_SHIFT;
56 /* PEX(1) PEX(2) CPRI 2 CPRI 1 */
67 QIXIS_WRITE_I2C(brdcfg[4], 0x03);
70 /* PEX(1) PEX(2) SGMII1 CPRI 1 */
81 QIXIS_WRITE_I2C(brdcfg[4], 0x01);
84 /* PEX(1) PEX(2) SGMII1 SGMII2 */
87 QIXIS_WRITE_I2C(brdcfg[4], 0x00);
90 /* PEX(1) SGMII2 CPRI 2 CPRI 1 */
101 QIXIS_WRITE_I2C(brdcfg[4], 0x07);
104 /* PEX(1) SGMII2 SGMII1 CPRI 1 */
115 QIXIS_WRITE_I2C(brdcfg[4], 0x05);
118 /* SGMII1 SGMII2 CPRI 2 CPRI 1 */
124 QIXIS_WRITE_I2C(brdcfg[4], 0x0F);
133 /* Configure DSP DDR controller */
134 void dsp_ddr_configure(void)
137 *There are separate DDR-controllers for DSP and PowerPC side DDR.
138 *copy the ddr controller settings from PowerPC side DDR controller
139 *to the DSP DDR controller as connected DDR memories are similar.
141 struct ccsr_ddr __iomem *pa_ddr =
142 (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
143 struct ccsr_ddr temp_ddr;
144 struct ccsr_ddr __iomem *dsp_ddr =
145 (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR;
147 memcpy(&temp_ddr, pa_ddr, sizeof(struct ccsr_ddr));
148 temp_ddr.cs0_bnds = CONFIG_SYS_DDR1_CS0_BNDS;
149 temp_ddr.sdram_cfg &= ~SDRAM_CFG_MEM_EN;
150 memcpy(dsp_ddr, &temp_ddr, sizeof(struct ccsr_ddr));
151 dsp_ddr->sdram_cfg |= SDRAM_CFG_MEM_EN;
154 int board_early_init_r(void)
156 #ifdef CONFIG_MTD_NOR_FLASH
157 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
158 int flash_esel = find_tlb_idx((void *)flashbase, 1);
161 * Remap Boot flash region to caching-inhibited
162 * so that flash can be erased properly.
165 /* Flush d-cache and invalidate i-cache of any FLASH data */
169 if (flash_esel == -1) {
170 /* very unlikely unless something is messed up */
171 puts("Error: Could not find TLB for FLASH BASE\n");
172 flash_esel = 2; /* give our best effort to continue */
174 /* invalidate existing TLB entry for flash */
175 disable_tlb(flash_esel);
178 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
179 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
180 0, flash_esel, BOOKE_PAGESZ_64M, 1);
182 set_tlb(1, flashbase + 0x4000000,
183 CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000,
184 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
185 0, flash_esel+1, BOOKE_PAGESZ_64M, 1);
187 board_config_serdes_mux();
193 void pci_init_board(void)
195 fsl_pcie_init_board(0);
197 #endif /* ifdef CONFIG_PCI */
201 struct cpu_type *cpu;
205 printf("Board: %sQDS\n", cpu->name);
207 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x,\n",
208 QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver));
210 sw = QIXIS_READ(brdcfg[0]);
211 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
213 printf("IFC chip select:");
225 printf("Invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
232 int board_eth_init(bd_t *bis)
234 #ifdef CONFIG_TSEC_ENET
235 struct fsl_pq_mdio_info mdio_info;
236 struct tsec_info_struct tsec_info[4];
240 SET_STD_TSEC_INFO(tsec_info[num], 1);
246 SET_STD_TSEC_INFO(tsec_info[num], 2);
250 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
251 mdio_info.name = DEFAULT_MII_NAME;
253 fsl_pq_mdio_init(bis, &mdio_info);
254 tsec_eth_init(bis, tsec_info, num);
264 #define USBMUX_SEL_MASK 0xc0
265 #define USBMUX_SEL_UART2 0xc0
266 #define USBMUX_SEL_USB 0x40
267 #define SPIMUX_SEL_UART3 0x80
268 #define GPS_MUX_SEL_GPS 0x40
270 #define TSEC_1588_CLKIN_MASK 0x03
271 #define CON_XCVR_REF_CLK 0x00
273 int misc_init_r(void)
276 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
277 u32 porbmsr = in_be32(&gur->porbmsr);
278 u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
280 /*Configure 1588 clock-in source from RF Card*/
281 val = QIXIS_READ_I2C(brdcfg[5]);
282 QIXIS_WRITE_I2C(brdcfg[5],
283 (val & ~(TSEC_1588_CLKIN_MASK)) | CON_XCVR_REF_CLK);
285 if (hwconfig("uart2") && hwconfig("usb1")) {
286 printf("UART2 and USB cannot work together on the board\n");
287 printf("Remove one from hwconfig and reset\n");
289 if (hwconfig("uart2")) {
290 val = QIXIS_READ_I2C(brdcfg[5]);
291 QIXIS_WRITE_I2C(brdcfg[5],
292 (val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_UART2);
293 clrbits_be32(&gur->pmuxcr3,
294 MPC85xx_PMUXCR3_USB_SEL_MASK);
295 setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART2_SEL);
297 /* By default USB should be selected.
298 * Programming FPGA to select USB. */
299 val = QIXIS_READ_I2C(brdcfg[5]);
300 QIXIS_WRITE_I2C(brdcfg[5],
301 (val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_USB);
306 if (hwconfig("sim")) {
307 if (romloc == PORBMSR_ROMLOC_NAND_2K ||
308 romloc == PORBMSR_ROMLOC_NOR ||
309 romloc == PORBMSR_ROMLOC_SPI) {
311 val = QIXIS_READ_I2C(brdcfg[3]);
312 QIXIS_WRITE_I2C(brdcfg[3], val|0x10);
313 clrbits_be32(&gur->pmuxcr,
314 MPC85xx_PMUXCR0_SIM_SEL_MASK);
315 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR0_SIM_SEL);
319 if (hwconfig("uart3")) {
320 if (romloc == PORBMSR_ROMLOC_NAND_2K ||
321 romloc == PORBMSR_ROMLOC_NOR ||
322 romloc == PORBMSR_ROMLOC_SDHC) {
324 /* UART3 and SPI1 (Flashes) are muxed together */
325 val = QIXIS_READ_I2C(brdcfg[3]);
326 QIXIS_WRITE_I2C(brdcfg[3], (val | SPIMUX_SEL_UART3));
327 clrbits_be32(&gur->pmuxcr3,
328 MPC85xx_PMUXCR3_UART3_SEL_MASK);
329 setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART3_SEL);
331 /* MUX to select UART3 connection to J24 header
333 val = QIXIS_READ_I2C(brdcfg[6]);
335 QIXIS_WRITE_I2C(brdcfg[6],
336 (val | GPS_MUX_SEL_GPS));
338 QIXIS_WRITE_I2C(brdcfg[6],
339 (val & ~(GPS_MUX_SEL_GPS)));
345 void fdt_del_node_compat(void *blob, const char *compatible)
348 int off = fdt_node_offset_by_compatible(blob, -1, compatible);
350 printf("WARNING: could not find compatible node %s: %s.\n",
351 compatible, fdt_strerror(off));
354 err = fdt_del_node(blob, off);
356 printf("WARNING: could not remove %s: %s.\n",
357 compatible, fdt_strerror(err));
361 #if defined(CONFIG_OF_BOARD_SETUP)
362 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
363 static const struct node_info nodes[] = {
364 { "cfi-flash", MTD_DEV_TYPE_NOR, },
365 { "fsl,ifc-nand", MTD_DEV_TYPE_NAND, },
368 int ft_board_setup(void *blob, bd_t *bd)
373 ft_cpu_setup(blob, bd);
375 base = env_get_bootm_low();
376 size = env_get_bootm_size();
378 #if defined(CONFIG_PCI)
382 fdt_fixup_memory(blob, (u64)base, (u64)size);
383 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
384 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
387 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
388 u32 porbmsr = in_be32(&gur->porbmsr);
389 u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
391 if (!(hwconfig("uart2") && hwconfig("usb1"))) {
392 /* If uart2 is there in hwconfig remove usb node from
395 if (hwconfig("uart2")) {
396 /* remove dts usb node */
397 fdt_del_node_compat(blob, "fsl-usb2-dr");
399 fsl_fdt_fixup_dr_usb(blob, bd);
400 fdt_del_node_and_alias(blob, "serial2");
404 if (hwconfig("uart3")) {
405 if (romloc == PORBMSR_ROMLOC_NAND_2K ||
406 romloc == PORBMSR_ROMLOC_NOR ||
407 romloc == PORBMSR_ROMLOC_SDHC)
408 /* Delete SPI node from the device tree */
409 fdt_del_node_and_alias(blob, "spi1");
411 fdt_del_node_and_alias(blob, "serial3");
413 if (hwconfig("sim")) {
414 if (romloc == PORBMSR_ROMLOC_NAND_2K ||
415 romloc == PORBMSR_ROMLOC_NOR ||
416 romloc == PORBMSR_ROMLOC_SPI) {
418 /* remove dts sdhc node */
419 fdt_del_node_compat(blob, "fsl,esdhc");
420 } else if (romloc == PORBMSR_ROMLOC_SDHC) {
422 /* remove dts sim node */
423 fdt_del_node_compat(blob, "fsl,sim-v1.0");
424 printf("SIM & SDHC can't work together on the board");
425 printf("\nRemove sim from hwconfig and reset\n");