2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/processor.h>
26 #include <asm/cache.h>
27 #include <asm/immap_85xx.h>
31 #include <fdt_support.h>
36 #include <asm/fsl_ifc.h>
39 #include <asm/fsl_ddr_sdram.h>
43 #include <asm/fsl_pci.h>
46 #include "../common/qixis.h"
47 DECLARE_GLOBAL_DATA_PTR;
50 int board_early_init_f(void)
52 struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR;
54 setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
59 void board_config_serdes_mux(void)
61 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
62 u32 pordevsr = in_be32(&gur->pordevsr);
63 u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
64 MPC85xx_PORDEVSR_IO_SEL_SHIFT;
67 /* PEX(1) PEX(2) CPRI 2 CPRI 1 */
78 QIXIS_WRITE_I2C(brdcfg[4], 0x03);
81 /* PEX(1) PEX(2) SGMII1 CPRI 1 */
92 QIXIS_WRITE_I2C(brdcfg[4], 0x01);
95 /* PEX(1) PEX(2) SGMII1 SGMII2 */
98 QIXIS_WRITE_I2C(brdcfg[4], 0x00);
101 /* PEX(1) SGMII2 CPRI 2 CPRI 1 */
112 QIXIS_WRITE_I2C(brdcfg[4], 0x07);
115 /* PEX(1) SGMII2 SGMII1 CPRI 1 */
126 QIXIS_WRITE_I2C(brdcfg[4], 0x05);
129 /* SGMII1 SGMII2 CPRI 2 CPRI 1 */
135 QIXIS_WRITE_I2C(brdcfg[4], 0x0F);
144 int board_early_init_r(void)
146 #ifndef CONFIG_SYS_NO_FLASH
147 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
148 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
151 * Remap Boot flash region to caching-inhibited
152 * so that flash can be erased properly.
155 /* Flush d-cache and invalidate i-cache of any FLASH data */
159 /* invalidate existing TLB entry for flash */
160 disable_tlb(flash_esel);
162 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
163 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
164 0, flash_esel, BOOKE_PAGESZ_64M, 1);
166 set_tlb(1, flashbase + 0x4000000,
167 CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000,
168 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
169 0, flash_esel+1, BOOKE_PAGESZ_64M, 1);
171 board_config_serdes_mux();
176 void pci_init_board(void)
178 fsl_pcie_init_board(0);
180 #endif /* ifdef CONFIG_PCI */
184 struct cpu_type *cpu;
188 printf("Board: %sQDS\n", cpu->name);
190 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x,\n",
191 QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver));
193 sw = QIXIS_READ(brdcfg[0]);
194 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
196 printf("IFC chip select:");
208 printf("Invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
215 #ifdef CONFIG_TSEC_ENET
216 int board_eth_init(bd_t *bis)
218 struct fsl_pq_mdio_info mdio_info;
219 struct tsec_info_struct tsec_info[4];
223 SET_STD_TSEC_INFO(tsec_info[num], 1);
229 SET_STD_TSEC_INFO(tsec_info[num], 2);
233 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
234 mdio_info.name = DEFAULT_MII_NAME;
236 fsl_pq_mdio_init(bis, &mdio_info);
237 tsec_eth_init(bis, tsec_info, num);
247 #define USBMUX_SEL_MASK 0xc0
248 #define USBMUX_SEL_UART2 0xc0
249 #define USBMUX_SEL_USB 0x40
250 #define SPIMUX_SEL_UART3 0x80
251 #define GPS_MUX_SEL_GPS 0x40
253 #define TSEC_1588_CLKIN_MASK 0x03
254 #define CON_XCVR_REF_CLK 0x00
256 int misc_init_r(void)
259 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
260 u32 porbmsr = in_be32(&gur->porbmsr);
261 u32 romloc = (porbmsr >> MPC85XX_PORBMSR_ROMLOC_SHIFT) & 0xf;
263 /*Configure 1588 clock-in source from RF Card*/
264 val = QIXIS_READ_I2C(brdcfg[5]);
265 QIXIS_WRITE_I2C(brdcfg[5],
266 (val & ~(TSEC_1588_CLKIN_MASK)) | CON_XCVR_REF_CLK);
268 if (hwconfig("uart2") && hwconfig("usb1")) {
269 printf("UART2 and USB cannot work together on the board\n");
270 printf("Remove one from hwconfig and reset\n");
272 if (hwconfig("uart2")) {
273 val = QIXIS_READ_I2C(brdcfg[5]);
274 QIXIS_WRITE_I2C(brdcfg[5],
275 (val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_UART2);
276 clrbits_be32(&gur->pmuxcr3,
277 MPC85xx_PMUXCR3_USB_SEL_MASK);
278 setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART2_SEL);
280 /* By default USB should be selected.
281 * Programming FPGA to select USB. */
282 val = QIXIS_READ_I2C(brdcfg[5]);
283 QIXIS_WRITE_I2C(brdcfg[5],
284 (val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_USB);
289 if (hwconfig("sim")) {
290 if (romloc == PORBMSR_ROMLOC_NAND_2K ||
291 romloc == PORBMSR_ROMLOC_NOR ||
292 romloc == PORBMSR_ROMLOC_SPI) {
294 val = QIXIS_READ_I2C(brdcfg[3]);
295 QIXIS_WRITE_I2C(brdcfg[3], val|0x10);
296 clrbits_be32(&gur->pmuxcr,
297 MPC85xx_PMUXCR0_SIM_SEL_MASK);
298 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR0_SIM_SEL);
302 if (hwconfig("uart3")) {
303 if (romloc == PORBMSR_ROMLOC_NAND_2K ||
304 romloc == PORBMSR_ROMLOC_NOR ||
305 romloc == PORBMSR_ROMLOC_SDHC) {
307 /* UART3 and SPI1 (Flashes) are muxed together */
308 val = QIXIS_READ_I2C(brdcfg[3]);
309 QIXIS_WRITE_I2C(brdcfg[3], (val | SPIMUX_SEL_UART3));
310 clrbits_be32(&gur->pmuxcr3,
311 MPC85xx_PMUXCR3_UART3_SEL_MASK);
312 setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART3_SEL);
314 /* MUX to select UART3 connection to J24 header
316 val = QIXIS_READ_I2C(brdcfg[6]);
318 QIXIS_WRITE_I2C(brdcfg[6],
319 (val | GPS_MUX_SEL_GPS));
321 QIXIS_WRITE_I2C(brdcfg[6],
322 (val & ~(GPS_MUX_SEL_GPS)));
328 void fdt_del_node_compat(void *blob, const char *compatible)
331 int off = fdt_node_offset_by_compatible(blob, -1, compatible);
333 printf("WARNING: could not find compatible node %s: %s.\n",
334 compatible, fdt_strerror(off));
337 err = fdt_del_node(blob, off);
339 printf("WARNING: could not remove %s: %s.\n",
340 compatible, fdt_strerror(err));
344 #if defined(CONFIG_OF_BOARD_SETUP)
345 void ft_board_setup(void *blob, bd_t *bd)
350 ft_cpu_setup(blob, bd);
352 base = getenv_bootm_low();
353 size = getenv_bootm_size();
355 #if defined(CONFIG_PCI)
359 fdt_fixup_memory(blob, (u64)base, (u64)size);
361 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
362 u32 porbmsr = in_be32(&gur->porbmsr);
363 u32 romloc = (porbmsr >> MPC85XX_PORBMSR_ROMLOC_SHIFT) & 0xf;
365 if (!(hwconfig("uart2") && hwconfig("usb1"))) {
366 /* If uart2 is there in hwconfig remove usb node from
369 if (hwconfig("uart2")) {
370 /* remove dts usb node */
371 fdt_del_node_compat(blob, "fsl-usb2-dr");
373 fdt_fixup_dr_usb(blob, bd);
374 fdt_del_node_and_alias(blob, "serial2");
378 if (hwconfig("uart3")) {
379 if (romloc == PORBMSR_ROMLOC_NAND_2K ||
380 romloc == PORBMSR_ROMLOC_NOR ||
381 romloc == PORBMSR_ROMLOC_SDHC)
382 /* Delete SPI node from the device tree */
383 fdt_del_node_and_alias(blob, "spi1");
385 fdt_del_node_and_alias(blob, "serial3");
387 if (hwconfig("sim")) {
388 if (romloc == PORBMSR_ROMLOC_NAND_2K ||
389 romloc == PORBMSR_ROMLOC_NOR ||
390 romloc == PORBMSR_ROMLOC_SPI) {
392 /* remove dts sdhc node */
393 fdt_del_node_compat(blob, "fsl,esdhc");
394 } else if (romloc == PORBMSR_ROMLOC_SDHC) {
396 /* remove dts sim node */
397 fdt_del_node_compat(blob, "fsl,sim-v1.0");
398 printf("SIM & SDHC can't work together on the board");
399 printf("\nRemove sim from hwconfig and reset\n");