1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2013 Freescale Semiconductor, Inc.
11 #include <linux/compiler.h>
12 #include <asm/fsl_law.h>
13 #include <fsl_ddr_sdram.h>
14 #include <asm/global_data.h>
15 #include <linux/delay.h>
17 DECLARE_GLOBAL_DATA_PTR;
20 * Fixed sdram init -- doesn't use serial presence detect.
22 static void sdram_init(void)
24 struct ccsr_ddr __iomem *ddr =
25 (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
27 __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
28 __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
29 #if CONFIG_CHIP_SELECTS_PER_CTRL > 1
30 __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
31 __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
33 __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3);
34 __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0);
35 __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1);
36 __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2);
38 __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
39 __raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode);
40 __raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2);
42 __raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval);
43 __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
44 __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl);
46 __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl);
47 __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
48 __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
49 __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
51 /* Set, but do not enable the memory */
52 __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg);
54 asm volatile("sync;isync");
57 /* Let the controller go */
58 out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
60 set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1);
63 void board_init_f(ulong bootflag)
66 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
68 /* initialize selected port with appropriate baud rate */
69 plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
71 gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
73 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
74 gd->bus_clk / 16 / CONFIG_BAUDRATE);
76 puts("\nNAND boot... ");
78 /* Initialize the DDR3 */
81 /* copy code to RAM and jump to it - this should not return */
82 /* NOTE - code has to be copied out of NAND buffer before
83 * other blocks can be read.
85 relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
88 void board_init_r(gd_t *gd, ulong dest_addr)
96 NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
98 NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
101 void puts(const char *str)