1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright 2013 Freescale Semiconductor, Inc.
6 #include <clock_legacy.h>
9 #include <env_internal.h>
16 #include "../common/qixis.h"
17 #include "b4860qds_qixis.h"
19 DECLARE_GLOBAL_DATA_PTR;
21 phys_size_t get_effective_memsize(void)
23 return CONFIG_SYS_L3_SIZE;
26 unsigned long get_board_sys_clk(void)
28 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
30 switch ((sysclk_conf & 0x0C) >> 2) {
41 unsigned long get_board_ddr_clk(void)
43 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
45 switch (ddrclk_conf & 0x03) {
56 void board_init_f(ulong bootflag)
58 u32 plat_ratio, sys_clk, uart_clk;
59 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
61 /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
62 memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
64 /* Update GD pointer */
65 gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
67 /* compiler optimization barrier needed for GCC >= 3.4 */
68 __asm__ __volatile__("" : : : "memory");
72 /* initialize selected port with appropriate baud rate */
73 sys_clk = get_board_sys_clk();
74 plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
75 uart_clk = sys_clk * plat_ratio / 2;
77 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
78 uart_clk / 16 / CONFIG_BAUDRATE);
80 relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
83 void board_init_r(gd_t *gd, ulong dest_addr)
87 bd = (bd_t *)(gd + sizeof(gd_t));
88 memset(bd, 0, sizeof(bd_t));
90 bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
91 bd->bi_memsize = CONFIG_SYS_L3_SIZE;
95 mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
96 CONFIG_SPL_RELOC_MALLOC_SIZE);
97 gd->flags |= GD_FLG_FULL_MALLOC_INIT;
99 #ifndef CONFIG_SPL_NAND_BOOT
103 /* relocate environment function pointers etc. */
104 nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
105 (uchar *)SPL_ENV_ADDR);
106 gd->env_addr = (ulong)(SPL_ENV_ADDR);
107 gd->env_valid = ENV_VALID;
116 #ifdef CONFIG_SPL_NAND_BOOT