1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2012 Freescale Semiconductor, Inc.
4 * Author: Sandeep Kumar Singh <sandeep@freescale.com>
7 /* This file is based on board/freescale/corenet_ds/eth_superhydra.c */
10 * This file handles the board muxing between the Fman Ethernet MACs and
11 * the RGMII/SGMII/XGMII PHYs on a Freescale B4860 "Centaur". The SGMII
12 * PHYs are the two on-board 1Gb ports. There are no RGMII PHY on board.
13 * The 10Gb XGMII PHY is provided via the XAUI riser card. There is only
14 * one Fman device on B4860. The SERDES configuration is used to determine
15 * where the SGMII and XAUI cards exist, and also which Fman MACs are routed
16 * to which PHYs. So for a given Fman MAC, there is one and only PHY it
17 * connects to. MACs cannot be routed to PHYs dynamically. This configuration
18 * is done at boot time by reading SERDES protocol from RCW.
23 #include <asm/fsl_serdes.h>
27 #include <fdt_support.h>
28 #include <fsl_dtsec.h>
30 #include "../common/ngpixis.h"
31 #include "../common/fman.h"
32 #include "../common/qixis.h"
33 #include "b4860qds_qixis.h"
35 #define EMI_NONE 0xFFFFFFFF
37 #ifdef CONFIG_FMAN_ENET
40 * Mapping of all 16 SERDES lanes to board slots. A value n(>0) will mean that
41 * lane at index is mapped to slot number n. A value of '0' will mean
42 * that the mapping must be determined dynamically, or that the lane maps to
43 * something other than a board slot
45 static u8 lane_to_slot[] = {
53 * This function initializes the lane_to_slot[] array. It reads RCW to check
54 * if Serdes2{E,F,G,H} is configured as slot 2 or as SFP and initializes
55 * lane_to_slot[] accordingly
57 static void initialize_lane_to_slot(void)
59 unsigned int serdes2_prtcl;
60 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
61 serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
62 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
63 serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
64 debug("Initializing lane to slot: Serdes2 protocol: %x\n",
67 switch (serdes2_prtcl) {
73 * Lanes: A,B,C,D: SGMII
83 * Lanes: E,F,G,H: XAUI2
89 * Lanes: A,B,C,D: SGMII
90 * Lanes: E,F,G,H: XAUI2
96 * Lanes: A,B,C,D: XAUI2
97 * Lanes: E,F,G,H: XAUI2
105 * Lanes: E,F,G,H: XAUI2
111 * Lanes: A,B,C,D: PCI
112 * Lanes: E,F,G,H: XAUI2
121 * Lanes: A,B,C,D: PCI
122 * Lanes: E,F: SGMII 3&4
131 * Lanes: E,F,G,H: XAUI2
133 lane_to_slot[12] = 2;
134 lane_to_slot[13] = lane_to_slot[12];
135 lane_to_slot[14] = lane_to_slot[12];
136 lane_to_slot[15] = lane_to_slot[12];
140 printf("Fman: Unsupported SerDes2 Protocol 0x%02x\n",
147 #endif /* #ifdef CONFIG_FMAN_ENET */
149 int board_eth_init(bd_t *bis)
151 #ifdef CONFIG_FMAN_ENET
152 struct memac_mdio_info memac_mdio_info;
153 struct memac_mdio_info tg_memac_mdio_info;
155 unsigned int serdes1_prtcl, serdes2_prtcl;
158 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
159 serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
160 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
161 if (!serdes1_prtcl) {
162 printf("SERDES1 is not enabled\n");
165 serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
166 debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
168 serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
169 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
170 if (!serdes2_prtcl) {
171 printf("SERDES2 is not enabled\n");
174 serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
175 debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
177 printf("Initializing Fman\n");
179 initialize_lane_to_slot();
181 memac_mdio_info.regs =
182 (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
183 memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
185 /* Register the real 1G MDIO bus */
186 fm_memac_mdio_init(bis, &memac_mdio_info);
188 tg_memac_mdio_info.regs =
189 (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
190 tg_memac_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
192 /* Register the real 10G MDIO bus */
193 fm_memac_mdio_init(bis, &tg_memac_mdio_info);
196 * Program the two on board DTSEC PHY addresses assuming that they are
197 * all SGMII. RGMII is not supported on this board. Setting SGMII 5 and
198 * 6 to on board SGMII phys
200 fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
201 fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
203 switch (serdes1_prtcl) {
206 /* Serdes 1: A-B SGMII, Configuring DTSEC 5 and 6 */
207 debug("Set phy addresses for FM1_DTSEC5:%x, FM1_DTSEC6:%x\n",
208 CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR,
209 CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
210 fm_info_set_phy_address(FM1_DTSEC5,
211 CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
212 fm_info_set_phy_address(FM1_DTSEC6,
213 CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
215 #ifdef CONFIG_ARCH_B4420
218 /* Serdes 1: A-D SGMII, Configuring on board dual SGMII Phy */
219 debug("Set phy addresses for FM1_DTSEC3:%x, FM1_DTSEC4:%x\n",
220 CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR,
221 CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
222 /* Fixing Serdes clock by programming FPGA register */
223 QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
224 fm_info_set_phy_address(FM1_DTSEC3,
225 CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
226 fm_info_set_phy_address(FM1_DTSEC4,
227 CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
231 printf("Fman: Unsupported SerDes1 Protocol 0x%02x\n",
235 switch (serdes2_prtcl) {
238 debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n",
239 CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
240 fm_info_set_phy_address(FM1_DTSEC1,
241 CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
242 fm_info_set_phy_address(FM1_DTSEC2,
243 CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
244 fm_info_set_phy_address(FM1_DTSEC3,
245 CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR);
246 fm_info_set_phy_address(FM1_DTSEC4,
247 CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR);
251 debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n",
252 CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
253 fm_info_set_phy_address(FM1_DTSEC1,
254 CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
255 fm_info_set_phy_address(FM1_DTSEC2,
256 CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
257 fm_info_set_phy_address(FM1_DTSEC3,
258 CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR);
264 debug("Set phy addresses on SGMII Riser for FM1_DTSEC1:%x\n",
265 CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
266 fm_info_set_phy_address(FM1_DTSEC3,
267 CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
268 fm_info_set_phy_address(FM1_DTSEC4,
269 CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
271 * XFI does not need a PHY to work, but to make U-Boot
272 * happy, assign a fake PHY address for a XFI port.
274 fm_info_set_phy_address(FM1_10GEC1, 0);
275 fm_info_set_phy_address(FM1_10GEC2, 1);
278 /* XAUI in Slot1 and Slot2 */
279 debug("Set phy address of AMC2PEX-2S for FM1_10GEC1:%x\n",
280 CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
281 fm_info_set_phy_address(FM1_10GEC1,
282 CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
283 debug("Set phy address of AMC2PEX-2S for FM1_10GEC2:%x\n",
284 CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
285 fm_info_set_phy_address(FM1_10GEC2,
286 CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
290 debug("Sett phy address of AMC2PEX-2S for FM1_10GEC2:%x\n",
291 CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
292 fm_info_set_phy_address(FM1_10GEC2,
293 CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
296 printf("Fman: Unsupported SerDes2 Protocol 0x%02x\n",
301 /*set PHY address for QSGMII Riser Card on slot2*/
302 bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
303 qsgmii = is_qsgmii_riser_card(bus, PHY_BASE_ADDR, PORT_NUM, REGNUM);
306 switch (serdes2_prtcl) {
309 fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR);
310 fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 1);
317 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
318 int idx = i - FM1_DTSEC1;
320 switch (fm_info_get_enet_if(i)) {
321 case PHY_INTERFACE_MODE_SGMII:
323 miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
325 case PHY_INTERFACE_MODE_NONE:
326 fm_info_set_phy_address(i, 0);
329 printf("Fman1: DTSEC%u set to unknown interface %i\n",
330 idx + 1, fm_info_get_enet_if(i));
331 fm_info_set_phy_address(i, 0);
336 for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
337 int idx = i - FM1_10GEC1;
339 switch (fm_info_get_enet_if(i)) {
340 case PHY_INTERFACE_MODE_XGMII:
342 miiphy_get_dev_by_name
343 (DEFAULT_FM_TGEC_MDIO_NAME));
345 case PHY_INTERFACE_MODE_NONE:
346 fm_info_set_phy_address(i, 0);
349 printf("Fman1: TGEC%u set to unknown interface %i\n",
350 idx + 1, fm_info_get_enet_if(i));
351 fm_info_set_phy_address(i, 0);
359 return pci_eth_init(bis);
362 void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
363 enum fm_port port, int offset)
367 struct fixed_link f_link;
368 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
369 u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
371 prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
373 if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
374 phy = fm_info_get_phy_address(port);
376 sprintf(alias, "phy_sgmii_%x", phy);
377 fdt_set_phy_handle(fdt, compat, addr, alias);
378 fdt_status_okay_by_alias(fdt, alias);
379 } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
380 /* check if it's XFI interface for 10g */
399 f_link.phy_id = port;
401 f_link.link_speed = 10000;
403 f_link.asym_pause = 0;
405 fdt_delprop(fdt, offset, "phy-handle");
406 fdt_setprop(fdt, offset, "fixed-link", &f_link,
409 case 0x98: /* XAUI interface */
410 strcpy(alias, "phy_xaui_slot1");
411 fdt_status_okay_by_alias(fdt, alias);
413 strcpy(alias, "phy_xaui_slot2");
414 fdt_status_okay_by_alias(fdt, alias);
416 case 0x9e: /* XAUI interface */
420 strcpy(alias, "phy_xaui_slot1");
421 fdt_status_okay_by_alias(fdt, alias);
423 case 0x97: /* XAUI interface */
425 strcpy(alias, "phy_xaui_slot2");
426 fdt_status_okay_by_alias(fdt, alias);
435 * Set status to disabled for unused ethernet node
437 void fdt_fixup_board_enet(void *fdt)
442 for (i = FM1_DTSEC1; i <= FM1_10GEC2; i++) {
443 switch (fm_info_get_enet_if(i)) {
444 case PHY_INTERFACE_MODE_NONE:
445 sprintf(alias, "ethernet%u", i);
446 fdt_status_disabled_by_alias(fdt, alias);