board/freescale/b4860qds/ddr.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright 2011-2012 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <i2c.h>
   8 #include <hwconfig.h>
   9 #include <fsl_ddr.h>
  10 #include <init.h>
  11 #include <log.h>
  12 #include <asm/mmu.h>
  13 #include <fsl_ddr_sdram.h>
  14 #include <fsl_ddr_dimm_params.h>
  15 #include <asm/fsl_law.h>
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 dimm_params_t ddr_raw_timing = {
  20         .n_ranks = 2,
  21         .rank_density = 2147483648u,
  22         .capacity = 4294967296u,
  23         .primary_sdram_width = 64,
  24         .ec_sdram_width = 8,
  25         .registered_dimm = 0,
  26         .mirrored_dimm = 1,
  27         .n_row_addr = 15,
  28         .n_col_addr = 10,
  29         .n_banks_per_sdram_device = 8,
  30         .edc_config = 2,        /* ECC */
  31         .burst_lengths_bitmask = 0x0c,
  32
  33         .tckmin_x_ps = 1071,
  34         .caslat_x = 0x2fe << 4, /* 5,6,7,8,9,10,11,13 */
  35         .taa_ps = 13910,
  36         .twr_ps = 15000,
  37         .trcd_ps = 13910,
  38         .trrd_ps = 6000,
  39         .trp_ps = 13910,
  40         .tras_ps = 34000,
  41         .trc_ps = 48910,
  42         .trfc_ps = 260000,
  43         .twtr_ps = 7500,
  44         .trtp_ps = 7500,
  45         .refresh_rate_ps = 7800000,
  46         .tfaw_ps = 35000,
  47 };
  48
  49 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
  50                 unsigned int controller_number,
  51                 unsigned int dimm_number)
  52 {
  53         const char dimm_model[] = "RAW timing DDR";
  54
  55         if ((controller_number == 0) && (dimm_number == 0)) {
  56                 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
  57                 memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
  58                 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
  59         }
  60
  61         return 0;
  62 }
  63
  64 struct board_specific_parameters {
  65         u32 n_ranks;
  66         u32 datarate_mhz_high;
  67         u32 clk_adjust;
  68         u32 wrlvl_start;
  69         u32 wrlvl_ctl_2;
  70         u32 wrlvl_ctl_3;
  71         u32 cpo;
  72         u32 write_data_delay;
  73         u32 force_2t;
  74 };
  75
  76 /*
  77  * This table contains all valid speeds we want to override with board
  78  * specific parameters. datarate_mhz_high values need to be in ascending order
  79  * for each n_ranks group.
  80  */
  81 static const struct board_specific_parameters udimm0[] = {
  82         /*
  83          * memory controller 0
  84          *   num|  hi|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
  85          * ranks| mhz|adjst| start |   ctl2    |  ctl3  |      |delay |
  86          */
  87         {2,  1350,    4,     7, 0x09080807, 0x07060607,   0xff,    2,  0},
  88         {2,  1666,    4,     7, 0x09080806, 0x06050607,   0xff,    2,  0},
  89         {2,  1900,    3,     7, 0x08070706, 0x06040507,   0xff,    2,  0},
  90         {1,  1350,    4,     7, 0x09080807, 0x07060607,   0xff,    2,  0},
  91         {1,  1700,    4,     7, 0x09080806, 0x06050607,   0xff,    2,  0},
  92         {1,  1900,    3,     7, 0x08070706, 0x06040507,   0xff,    2,  0},
  93         {}
  94 };
  95
  96 static const struct board_specific_parameters *udimms[] = {
  97         udimm0,
  98 };
  99
 100 void fsl_ddr_board_options(memctl_options_t *popts,
 101                                 dimm_params_t *pdimm,
 102                                 unsigned int ctrl_num)
 103 {
 104         const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
 105         ulong ddr_freq;
 106
 107         if (ctrl_num > 2) {
 108                 printf("Not supported controller number %d\n", ctrl_num);
 109                 return;
 110         }
 111         if (!pdimm->n_ranks)
 112                 return;
 113
 114         pbsp = udimms[0];
 115
 116
 117         /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
 118          * freqency and n_banks specified in board_specific_parameters table.
 119          */
 120         ddr_freq = get_ddr_freq(0) / 1000000;
 121         while (pbsp->datarate_mhz_high) {
 122                 if (pbsp->n_ranks == pdimm->n_ranks) {
 123                         if (ddr_freq <= pbsp->datarate_mhz_high) {
 124                                 popts->cpo_override = pbsp->cpo;
 125                                 popts->write_data_delay =
 126                                         pbsp->write_data_delay;
 127                                 popts->clk_adjust = pbsp->clk_adjust;
 128                                 popts->wrlvl_start = pbsp->wrlvl_start;
 129                                 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
 130                                 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
 131                                 popts->twot_en = pbsp->force_2t;
 132                                 goto found;
 133                         }
 134                         pbsp_highest = pbsp;
 135                 }
 136                 pbsp++;
 137         }
 138
 139         if (pbsp_highest) {
 140                 printf("Error: board specific timing not found "
 141                         "for data rate %lu MT/s\n"
 142                         "Trying to use the highest speed (%u) parameters\n",
 143                         ddr_freq, pbsp_highest->datarate_mhz_high);
 144                 popts->cpo_override = pbsp_highest->cpo;
 145                 popts->write_data_delay = pbsp_highest->write_data_delay;
 146                 popts->clk_adjust = pbsp_highest->clk_adjust;
 147                 popts->wrlvl_start = pbsp_highest->wrlvl_start;
 148                 popts->twot_en = pbsp_highest->force_2t;
 149         } else {
 150                 panic("DIMM is not supported by this board");
 151         }
 152 found:
 153         /*
 154          * Factors to consider for half-strength driver enable:
 155          *      - number of DIMMs installed
 156          */
 157         popts->half_strength_driver_enable = 0;
 158         /*
 159          * Write leveling override
 160          */
 161         popts->wrlvl_override = 1;
 162         popts->wrlvl_sample = 0xf;
 163
 164         /*
 165          * Rtt and Rtt_WR override
 166          */
 167         popts->rtt_override = 0;
 168
 169         /* Enable ZQ calibration */
 170         popts->zq_en = 1;
 171
 172         /* DHC_EN =1, ODT = 75 Ohm */
 173         popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
 174         popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
 175
 176         /* optimize cpo for erratum A-009942 */
 177         popts->cpo_sample = 0x3e;
 178 }
 179
 180 int dram_init(void)
 181 {
 182         phys_size_t dram_size;
 183
 184 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
 185         puts("Initializing....using SPD\n");
 186         dram_size = fsl_ddr_sdram();
 187 #else
 188         dram_size =  fsl_ddr_sdram_size();
 189 #endif
 190         dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 191         dram_size *= 0x100000;
 192
 193         gd->ram_size = dram_size;
 194
 195         return 0;
 196 }
 197
 198 unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
 199                           unsigned int dbw_cap_adj[])
 200 {
 201         int i, j;
 202         unsigned long long total_mem, current_mem_base, total_ctlr_mem;
 203         unsigned long long rank_density, ctlr_density = 0;
 204
 205         current_mem_base = 0ull;
 206         total_mem = 0;
 207         /*
 208          * This board has soldered DDR chips. DDRC1 has two rank.
 209          * DDRC2 has only one rank.
 210          * Assigning DDRC2 to lower address and DDRC1 to higher address.
 211          */
 212         if (pinfo->memctl_opts[0].memctl_interleaving) {
 213                 rank_density = pinfo->dimm_params[0][0].rank_density >>
 214                                         dbw_cap_adj[0];
 215                 ctlr_density = rank_density;
 216
 217                 debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
 218                       rank_density, ctlr_density);
 219                 for (i = CONFIG_SYS_NUM_DDR_CTLRS - 1; i >= 0; i--) {
 220                         switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
 221                         case FSL_DDR_CACHE_LINE_INTERLEAVING:
 222                         case FSL_DDR_PAGE_INTERLEAVING:
 223                         case FSL_DDR_BANK_INTERLEAVING:
 224                         case FSL_DDR_SUPERBANK_INTERLEAVING:
 225                                 total_ctlr_mem = 2 * ctlr_density;
 226                                 break;
 227                         default:
 228                                 panic("Unknown interleaving mode");
 229                         }
 230                         pinfo->common_timing_params[i].base_address =
 231                                                 current_mem_base;
 232                         pinfo->common_timing_params[i].total_mem =
 233                                                 total_ctlr_mem;
 234                         total_mem = current_mem_base + total_ctlr_mem;
 235                         debug("ctrl %d base 0x%llx\n", i, current_mem_base);
 236                         debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
 237                 }
 238         } else {
 239                 /*
 240                  * Simple linear assignment if memory
 241                  * controllers are not interleaved.
 242                  */
 243                 for (i = CONFIG_SYS_NUM_DDR_CTLRS - 1; i >= 0; i--) {
 244                         total_ctlr_mem = 0;
 245                         pinfo->common_timing_params[i].base_address =
 246                                                 current_mem_base;
 247                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 248                                 /* Compute DIMM base addresses. */
 249                                 unsigned long long cap =
 250                                         pinfo->dimm_params[i][j].capacity;
 251                                 pinfo->dimm_params[i][j].base_address =
 252                                         current_mem_base;
 253                                 debug("ctrl %d dimm %d base 0x%llx\n",
 254                                       i, j, current_mem_base);
 255                                 current_mem_base += cap;
 256                                 total_ctlr_mem += cap;
 257                         }
 258                         debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
 259                         pinfo->common_timing_params[i].total_mem =
 260                                                         total_ctlr_mem;
 261                         total_mem += total_ctlr_mem;
 262                 }
 263         }
 264         debug("Total mem by %s is 0x%llx\n", __func__, total_mem);
 265
 266         return total_mem;
 267 }