2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Derived from FADS860T definitions by Magnus Damm, Helmut Buchsbaum,
8 * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
10 * This header file contains values common to all FADS family boards.
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 /****************************************************************************
32 * Flash Memory Map as used by U-Boot:
34 * Start Address Length
35 * +-----------------------+ 0xFE00_0000 Start of Flash -----------------
36 * | | 0xFE00_0100 Reset Vector
40 * +-----------------------+ 0xFE04_0000 (sector border)
43 * | U-Boot environment |
46 * +=======================+ 0xFE08_0000 (sector border) -----------------
47 * | Available | | Applications
50 *****************************************************************************/
53 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
55 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
58 #define CONFIG_ENV_OVERWRITE
60 #define CONFIG_NFSBOOTCOMMAND \
62 "setenv bootargs root=/dev/nfs rw nfsroot=$rootpath " \
63 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
66 #define CONFIG_BOOTCOMMAND \
67 "setenv bootargs root=/dev/mtdblock2 rw mtdparts=phys:1280K(ROM)ro,-(root) "\
68 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
71 #undef CONFIG_BOOTARGS
73 #undef CONFIG_WATCHDOG /* watchdog disabled */
75 #if !defined(CONFIG_MPC885ADS)
76 #define CONFIG_BZIP2 /* include support for bzip2 compressed images */
80 * New MPC86xADS and MPC885ADS provide two Ethernet connectivity options:
81 * 10Mbit/s on SCC and 100Mbit/s on FEC. FADS provides SCC Ethernet on
82 * motherboard and FEC Ethernet on daughterboard. All new PQ1 chips have
83 * got FEC so FEC is the default.
86 #undef CONFIG_SCC1_ENET /* Disable SCC1 ethernet */
87 #define CONFIG_FEC_ENET /* Use FEC ethernet */
88 #else /* Old ADS has not got FEC option */
89 #define CONFIG_SCC1_ENET /* Use SCC1 ethernet */
90 #undef CONFIG_FEC_ENET /* No FEC ethernet */
91 #endif /* !CONFIG_ADS */
93 #if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
94 #error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
97 #ifdef CONFIG_FEC_ENET
98 #define CFG_DISCOVER_PHY
105 #define CONFIG_BOOTP_BOOTFILESIZE
106 #define CONFIG_BOOTP_BOOTPATH
107 #define CONFIG_BOOTP_GATEWAY
108 #define CONFIG_BOOTP_HOSTNAME
111 #if !defined(FADS_COMMANDS_ALREADY_DEFINED)
113 * Command line configuration.
115 #include <config_cmd_default.h>
117 #define CONFIG_CMD_ASKENV
118 #define CONFIG_CMD_DHCP
119 #define CONFIG_CMD_ECHO
120 #define CONFIG_CMD_IMMAP
121 #define CONFIG_CMD_JFFS2
122 #define CONFIG_CMD_MII
123 #define CONFIG_CMD_PCMCIA
124 #define CONFIG_CMD_PING
130 * Miscellaneous configurable options
132 #define CFG_PROMPT "=>" /* Monitor Command Prompt */
133 #define CFG_HUSH_PARSER
134 #define CFG_PROMPT_HUSH_PS2 "> "
135 #define CFG_LONGHELP /* #undef to save memory */
136 #if defined(CONFIG_CMD_KGDB)
137 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
139 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
141 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
142 #define CFG_MAXARGS 16 /* max number of command args */
143 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
145 #define CFG_LOAD_ADDR 0x00100000
147 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
149 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
152 * Low Level Configuration Settings
153 * (address mappings, register initial values, etc.)
154 * You should know what you are doing if you make changes here.
157 /*-----------------------------------------------------------------------
158 * Internal Memory Mapped Register
160 #define CFG_IMMR 0xFF000000
162 /*-----------------------------------------------------------------------
163 * Definitions for initial stack pointer and data area (in DPRAM)
165 #define CFG_INIT_RAM_ADDR CFG_IMMR
166 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
167 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
168 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
169 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
171 /*-----------------------------------------------------------------------
172 * Start addresses for the final memory configuration
173 * (Set up by the startup code)
174 * Please note that CFG_SDRAM_BASE _must_ start at 0
176 #define CFG_SDRAM_BASE 0x00000000
177 #if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC885ADS) /* New ADS or Duet */
178 #define CFG_SDRAM_SIZE 0x00800000 /* 8 Mbyte */
181 * 1000 factor s -> ms
182 * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
183 * 4 Number of refresh cycles per period
184 * 64 Refresh cycle in ms per number of rows
186 #define CFG_PTA_PER_CLK ((2048 * 64 * 1000) / (4 * 64))
187 #elif defined(CONFIG_FADS) /* Old/new FADS */
188 #define CFG_SDRAM_SIZE 0x00400000 /* 4 Mbyte */
190 #define CFG_SDRAM_SIZE 0x00000000 /* No SDRAM */
193 #define CFG_MEMTEST_START 0x0100000 /* memtest works on */
195 #define CFG_MEMTEST_END CFG_SDRAM_SIZE /* 1 ... SDRAM_SIZE */
197 #define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
198 #endif /* CFG_SDRAM_SIZE */
201 * For booting Linux, the board info and command line data
202 * have to be in the first 8 MB of memory, since this is
203 * the maximum mapped by the Linux kernel during initialization.
205 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
207 #define CFG_MONITOR_BASE TEXT_BASE
208 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 KB for monitor */
211 #define CFG_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */
213 #define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */
214 #endif /* CONFIG_BZIP2 */
216 /*-----------------------------------------------------------------------
219 #define CFG_FLASH_BASE CFG_MONITOR_BASE
220 #define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
222 #define CFG_MAX_FLASH_BANKS 4 /* max number of memory banks */
223 #define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
225 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
226 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
228 #define CFG_ENV_IS_IN_FLASH 1
229 #define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */
230 #define CFG_ENV_OFFSET CFG_ENV_SECT_SIZE
231 #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment */
232 #define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
234 #define CFG_DIRECT_FLASH_TFTP
236 #if defined(CONFIG_CMD_JFFS2)
242 /* No command line, one static partition, whole device */
243 #undef CONFIG_JFFS2_CMDLINE
244 #define CONFIG_JFFS2_DEV "nor0"
245 #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
246 #define CONFIG_JFFS2_PART_OFFSET 0x00000000
248 /* mtdparts command line support */
249 /* Note: fake mtd_id used, no linux mtd map file */
251 #define CONFIG_JFFS2_CMDLINE
252 #define MTDIDS_DEFAULT "nor0=fads0,nor1=fads-1,nor2=fads-2,nor3=fads-3"
253 #define MTDPARTS_DEFAULT "mtdparts=fads-0:-@1m(user1),fads-1:-(user2),fads-2:-(user3),fads-3:-(user4)"
256 #define CFG_JFFS2_SORT_FRAGMENTS
259 /*-----------------------------------------------------------------------
260 * Cache Configuration
262 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
263 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
265 /*-----------------------------------------------------------------------
268 #if defined(CONFIG_CMD_I2C)
269 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
270 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address defaults */
271 #define CFG_I2C_SLAVE 0x7F
274 /*-----------------------------------------------------------------------
275 * SYPCR - System Protection Control 11-9
276 * SYPCR can only be written once after reset!
277 *-----------------------------------------------------------------------
278 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
280 #if defined(CONFIG_WATCHDOG)
281 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
282 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
284 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
287 /*-----------------------------------------------------------------------
288 * SIUMCR - SIU Module Configuration 11-6
289 *-----------------------------------------------------------------------
290 * PCMCIA config., multi-function pin tri-state
292 #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
294 /*-----------------------------------------------------------------------
295 * TBSCR - Time Base Status and Control 11-26
296 *-----------------------------------------------------------------------
297 * Clear Reference Interrupt Status, Timebase freezing enabled
299 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
301 /*-----------------------------------------------------------------------
302 * PISCR - Periodic Interrupt Status and Control 11-31
303 *-----------------------------------------------------------------------
304 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
306 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
308 /*-----------------------------------------------------------------------
309 * SCCR - System Clock and reset Control Register 15-27
310 *-----------------------------------------------------------------------
311 * Set clock output, timebase and RTC source and divider,
312 * power management and some other internal clocks
314 #define SCCR_MASK SCCR_EBDF11
315 #define CFG_SCCR SCCR_TBS
317 /*-----------------------------------------------------------------------
318 * DER - Debug Enable Register
319 *-----------------------------------------------------------------------
320 * Set to zero to prevent the processor from entering debug mode
324 /* Because of the way the 860 starts up and assigns CS0 the entire
325 * address space, we have to set the memory controller differently.
326 * Normally, you write the option register first, and then enable the
327 * chip select by writing the base register. For CS0, you must write
328 * the base register first, followed by the option register.
332 * Init Memory Controller:
337 /* the other CS:s are determined by looking at parameters in BCSRx */
339 #define BCSR_ADDR ((uint) 0xFF080000)
341 #define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
343 /* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
344 #define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
346 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 8 Mbyte until detected */
347 #define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BR_BA_MSK) | BR_V )
349 /* BCSRx - Board Control and Status Registers */
350 #define CFG_OR1_PRELIM 0xFFFF8110 /* 64Kbyte address space */
351 #define CFG_BR1_PRELIM ((BCSR_ADDR) | BR_V)
354 * Internal Definitions
358 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
359 #define BOOTFLAG_WARM 0x02 /* Software reboot */
361 /* values according to the manual */
363 #define BCSR0 ((uint) (BCSR_ADDR + 0x00))
364 #define BCSR1 ((uint) (BCSR_ADDR + 0x04))
365 #define BCSR2 ((uint) (BCSR_ADDR + 0x08))
366 #define BCSR3 ((uint) (BCSR_ADDR + 0x0c))
367 #define BCSR4 ((uint) (BCSR_ADDR + 0x10))
370 * (F)ADS bitvalues by Helmut Buchsbaum
372 * See User's Manual for a proper
373 * description of the following structures
376 #define BCSR0_ERB ((uint)0x80000000)
377 #define BCSR0_IP ((uint)0x40000000)
378 #define BCSR0_BDIS ((uint)0x10000000)
379 #define BCSR0_BPS_MASK ((uint)0x0C000000)
380 #define BCSR0_ISB_MASK ((uint)0x01800000)
381 #define BCSR0_DBGC_MASK ((uint)0x00600000)
382 #define BCSR0_DBPC_MASK ((uint)0x00180000)
383 #define BCSR0_EBDF_MASK ((uint)0x00060000)
385 #define BCSR1_FLASH_EN ((uint)0x80000000)
386 #define BCSR1_DRAM_EN ((uint)0x40000000)
387 #define BCSR1_ETHEN ((uint)0x20000000)
388 #define BCSR1_IRDEN ((uint)0x10000000)
389 #define BCSR1_FLASH_CFG_EN ((uint)0x08000000)
390 #define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
391 #define BCSR1_BCSR_EN ((uint)0x02000000)
392 #define BCSR1_RS232EN_1 ((uint)0x01000000)
393 #define BCSR1_PCCEN ((uint)0x00800000)
394 #define BCSR1_PCCVCC0 ((uint)0x00400000)
395 #define BCSR1_PCCVPP_MASK ((uint)0x00300000)
396 #define BCSR1_DRAM_HALF_WORD ((uint)0x00080000)
397 #define BCSR1_RS232EN_2 ((uint)0x00040000)
398 #define BCSR1_SDRAM_EN ((uint)0x00020000)
399 #define BCSR1_PCCVCC1 ((uint)0x00010000)
401 #define BCSR1_PCCVCCON BCSR1_PCCVCC0
403 #define BCSR2_FLASH_PD_MASK ((uint)0xF0000000)
404 #define BCSR2_FLASH_PD_SHIFT 28
405 #define BCSR2_DRAM_PD_MASK ((uint)0x07800000)
406 #define BCSR2_DRAM_PD_SHIFT 23
407 #define BCSR2_EXTTOLI_MASK ((uint)0x00780000)
408 #define BCSR2_DBREVNR_MASK ((uint)0x00030000)
410 #define BCSR3_DBID_MASK ((ushort)0x3800)
411 #define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
412 #define BCSR3_BREVNR0 ((ushort)0x0080)
413 #define BCSR3_FLASH_PD_MASK ((ushort)0x0070)
414 #define BCSR3_BREVN1 ((ushort)0x0008)
415 #define BCSR3_BREVN2_MASK ((ushort)0x0003)
417 #define BCSR4_ETHLOOP ((uint)0x80000000)
418 #define BCSR4_TFPLDL ((uint)0x40000000)
419 #define BCSR4_TPSQEL ((uint)0x20000000)
420 #define BCSR4_SIGNAL_LAMP ((uint)0x10000000)
421 #if defined(CONFIG_MPC823)
422 #define BCSR4_USB_EN ((uint)0x08000000)
423 #define BCSR4_USB_SPEED ((uint)0x04000000)
424 #define BCSR4_VCCO ((uint)0x02000000)
425 #define BCSR4_VIDEO_ON ((uint)0x00800000)
426 #define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000)
427 #define BCSR4_VIDEO_RST ((uint)0x00200000)
428 #define BCSR4_MODEM_EN ((uint)0x00100000)
429 #define BCSR4_DATA_VOICE ((uint)0x00080000)
430 #elif defined(CONFIG_MPC850)
431 #define BCSR4_DATA_VOICE ((uint)0x00080000)
432 #elif defined(CONFIG_MPC860SAR)
433 #define BCSR4_UTOPIA_EN ((uint)0x08000000)
434 #else /* MPC860T and other chips with FEC */
435 #define BCSR4_FETH_EN ((uint)0x08000000)
436 #define BCSR4_FETHCFG0 ((uint)0x04000000)
437 #define BCSR4_FETHFDE ((uint)0x02000000)
438 #define BCSR4_FETHCFG1 ((uint)0x00400000)
439 #define BCSR4_FETHRST ((uint)0x00200000)
442 /* BSCR5 exists on MPC86xADS and MPC885ADS only */
444 #define CFG_PHYDEV_ADDR (BCSR_ADDR + 0x20000)
446 #define BCSR5 (CFG_PHYDEV_ADDR + 0x300)
448 #define BCSR5_MII2_EN 0x40
449 #define BCSR5_MII2_RST 0x20
450 #define BCSR5_T1_RST 0x10
451 #define BCSR5_ATM155_RST 0x08
452 #define BCSR5_ATM25_RST 0x04
453 #define BCSR5_MII1_EN 0x02
454 #define BCSR5_MII1_RST 0x01
456 /* We don't use the 8259.
458 #define NR_8259_INTS 0
460 /*-----------------------------------------------------------------------
462 *-----------------------------------------------------------------------
464 #define CFG_PCMCIA_MEM_ADDR (0xE0000000)
465 #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
466 #define CFG_PCMCIA_DMA_ADDR (0xE4000000)
467 #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
468 #define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
469 #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
470 #define CFG_PCMCIA_IO_ADDR (0xEC000000)
471 #define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
473 /*-----------------------------------------------------------------------
475 *-----------------------------------------------------------------------
477 #define CONFIG_MAC_PARTITION 1
478 #define CONFIG_DOS_PARTITION 1
479 #define CONFIG_ISO_PARTITION 1
482 #if 0 /* does not make sense when CONFIG_CMD_IDE is not enabled, too */
483 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
485 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
486 #undef CONFIG_IDE_LED /* LED for ide not supported */
487 #undef CONFIG_IDE_RESET /* reset for ide not supported */
489 #define CFG_IDE_MAXBUS 1 /* max. 2 IDE busses */
490 #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
492 #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
493 #define CFG_ATA_IDE0_OFFSET 0x0000
495 /* Offset for data I/O */
496 #define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
497 /* Offset for normal register accesses */
498 #define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
499 /* Offset for alternate registers */
500 #define CFG_ATA_ALT_OFFSET 0x0000
502 #define CONFIG_DISK_SPINUP_TIME 1000000
503 /* #undef CONFIG_DISK_SPINUP_TIME */ /* usin Compact Flash */