2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Derived from FADS860T definitions by Magnus Damm, Helmut Buchsbaum,
8 * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
10 * This header file contains values common to all FADS family boards.
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 /****************************************************************************
32 * Flash Memory Map as used by U-Boot:
34 * Start Address Length
35 * +-----------------------+ 0xFE00_0000 Start of Flash -----------------
36 * | | 0xFE00_0100 Reset Vector
40 * +-----------------------+ 0xFE04_0000 (sector border)
43 * | U-Boot environment |
46 * +=======================+ 0xFE08_0000 (sector border) -----------------
47 * | Available | | Applications
50 *****************************************************************************/
53 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
55 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
58 #define CONFIG_ENV_OVERWRITE
60 #define CONFIG_NFSBOOTCOMMAND \
62 "setenv bootargs root=/dev/nfs rw nfsroot=$rootpath " \
63 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
66 #define CONFIG_BOOTCOMMAND \
67 "setenv bootargs root=/dev/mtdblock2 rw mtdparts=phys:1280K(ROM)ro,-(root) "\
68 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
71 #undef CONFIG_BOOTARGS
73 #undef CONFIG_WATCHDOG /* watchdog disabled */
75 #if !defined(CONFIG_MPC885ADS)
76 #define CONFIG_BZIP2 /* include support for bzip2 compressed images */
80 * New MPC86xADS and MPC885ADS provide two Ethernet connectivity options:
81 * 10Mbit/s on SCC and 100Mbit/s on FEC. FADS provides SCC Ethernet on
82 * motherboard and FEC Ethernet on daughterboard. All new PQ1 chips have
83 * got FEC so FEC is the default.
86 #undef CONFIG_SCC1_ENET /* Disable SCC1 ethernet */
87 #define CONFIG_FEC_ENET /* Use FEC ethernet */
88 #else /* Old ADS has not got FEC option */
89 #define CONFIG_SCC1_ENET /* Use SCC1 ethernet */
90 #undef CONFIG_FEC_ENET /* No FEC ethernet */
91 #endif /* !CONFIG_ADS */
93 #if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
94 #error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
97 #ifdef CONFIG_FEC_ENET
98 #define CFG_DISCOVER_PHY
99 #define CONFIG_MII_INIT 1
106 #define CONFIG_BOOTP_BOOTFILESIZE
107 #define CONFIG_BOOTP_BOOTPATH
108 #define CONFIG_BOOTP_GATEWAY
109 #define CONFIG_BOOTP_HOSTNAME
112 #if !defined(FADS_COMMANDS_ALREADY_DEFINED)
114 * Command line configuration.
116 #include <config_cmd_default.h>
118 #define CONFIG_CMD_ASKENV
119 #define CONFIG_CMD_DHCP
120 #define CONFIG_CMD_ECHO
121 #define CONFIG_CMD_IMMAP
122 #define CONFIG_CMD_JFFS2
123 #define CONFIG_CMD_MII
124 #define CONFIG_CMD_PCMCIA
125 #define CONFIG_CMD_PING
131 * Miscellaneous configurable options
133 #define CFG_PROMPT "=>" /* Monitor Command Prompt */
134 #define CFG_HUSH_PARSER
135 #define CFG_PROMPT_HUSH_PS2 "> "
136 #define CFG_LONGHELP /* #undef to save memory */
137 #if defined(CONFIG_CMD_KGDB)
138 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
140 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
142 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
143 #define CFG_MAXARGS 16 /* max number of command args */
144 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
146 #define CFG_LOAD_ADDR 0x00100000
148 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
150 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
153 * Low Level Configuration Settings
154 * (address mappings, register initial values, etc.)
155 * You should know what you are doing if you make changes here.
158 /*-----------------------------------------------------------------------
159 * Internal Memory Mapped Register
161 #define CFG_IMMR 0xFF000000
163 /*-----------------------------------------------------------------------
164 * Definitions for initial stack pointer and data area (in DPRAM)
166 #define CFG_INIT_RAM_ADDR CFG_IMMR
167 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
168 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
169 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
170 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
172 /*-----------------------------------------------------------------------
173 * Start addresses for the final memory configuration
174 * (Set up by the startup code)
175 * Please note that CFG_SDRAM_BASE _must_ start at 0
177 #define CFG_SDRAM_BASE 0x00000000
178 #if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC885ADS) /* New ADS or Duet */
179 #define CFG_SDRAM_SIZE 0x00800000 /* 8 Mbyte */
182 * 1000 factor s -> ms
183 * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
184 * 4 Number of refresh cycles per period
185 * 64 Refresh cycle in ms per number of rows
187 #define CFG_PTA_PER_CLK ((2048 * 64 * 1000) / (4 * 64))
188 #elif defined(CONFIG_FADS) /* Old/new FADS */
189 #define CFG_SDRAM_SIZE 0x00400000 /* 4 Mbyte */
191 #define CFG_SDRAM_SIZE 0x00000000 /* No SDRAM */
194 #define CFG_MEMTEST_START 0x0100000 /* memtest works on */
196 #define CFG_MEMTEST_END CFG_SDRAM_SIZE /* 1 ... SDRAM_SIZE */
198 #define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
199 #endif /* CFG_SDRAM_SIZE */
202 * For booting Linux, the board info and command line data
203 * have to be in the first 8 MB of memory, since this is
204 * the maximum mapped by the Linux kernel during initialization.
206 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
208 #define CFG_MONITOR_BASE TEXT_BASE
209 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 KB for monitor */
212 #define CFG_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */
214 #define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */
215 #endif /* CONFIG_BZIP2 */
217 /*-----------------------------------------------------------------------
220 #define CFG_FLASH_BASE CFG_MONITOR_BASE
221 #define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
223 #define CFG_MAX_FLASH_BANKS 4 /* max number of memory banks */
224 #define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
226 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
227 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
229 #define CFG_ENV_IS_IN_FLASH 1
230 #define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */
231 #define CFG_ENV_OFFSET CFG_ENV_SECT_SIZE
232 #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment */
233 #define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
235 #define CFG_DIRECT_FLASH_TFTP
237 #if defined(CONFIG_CMD_JFFS2)
243 /* No command line, one static partition, whole device */
244 #undef CONFIG_JFFS2_CMDLINE
245 #define CONFIG_JFFS2_DEV "nor0"
246 #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
247 #define CONFIG_JFFS2_PART_OFFSET 0x00000000
249 /* mtdparts command line support */
250 /* Note: fake mtd_id used, no linux mtd map file */
252 #define CONFIG_JFFS2_CMDLINE
253 #define MTDIDS_DEFAULT "nor0=fads0,nor1=fads-1,nor2=fads-2,nor3=fads-3"
254 #define MTDPARTS_DEFAULT "mtdparts=fads-0:-@1m(user1),fads-1:-(user2),fads-2:-(user3),fads-3:-(user4)"
257 #define CFG_JFFS2_SORT_FRAGMENTS
260 /*-----------------------------------------------------------------------
261 * Cache Configuration
263 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
264 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
266 /*-----------------------------------------------------------------------
269 #if defined(CONFIG_CMD_I2C)
270 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
271 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address defaults */
272 #define CFG_I2C_SLAVE 0x7F
275 /*-----------------------------------------------------------------------
276 * SYPCR - System Protection Control 11-9
277 * SYPCR can only be written once after reset!
278 *-----------------------------------------------------------------------
279 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
281 #if defined(CONFIG_WATCHDOG)
282 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
283 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
285 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
288 /*-----------------------------------------------------------------------
289 * SIUMCR - SIU Module Configuration 11-6
290 *-----------------------------------------------------------------------
291 * PCMCIA config., multi-function pin tri-state
293 #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
295 /*-----------------------------------------------------------------------
296 * TBSCR - Time Base Status and Control 11-26
297 *-----------------------------------------------------------------------
298 * Clear Reference Interrupt Status, Timebase freezing enabled
300 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
302 /*-----------------------------------------------------------------------
303 * PISCR - Periodic Interrupt Status and Control 11-31
304 *-----------------------------------------------------------------------
305 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
307 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
309 /*-----------------------------------------------------------------------
310 * SCCR - System Clock and reset Control Register 15-27
311 *-----------------------------------------------------------------------
312 * Set clock output, timebase and RTC source and divider,
313 * power management and some other internal clocks
315 #define SCCR_MASK SCCR_EBDF11
316 #define CFG_SCCR SCCR_TBS
318 /*-----------------------------------------------------------------------
319 * DER - Debug Enable Register
320 *-----------------------------------------------------------------------
321 * Set to zero to prevent the processor from entering debug mode
325 /* Because of the way the 860 starts up and assigns CS0 the entire
326 * address space, we have to set the memory controller differently.
327 * Normally, you write the option register first, and then enable the
328 * chip select by writing the base register. For CS0, you must write
329 * the base register first, followed by the option register.
333 * Init Memory Controller:
338 /* the other CS:s are determined by looking at parameters in BCSRx */
340 #define BCSR_ADDR ((uint) 0xFF080000)
342 #define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
344 /* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
345 #define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
347 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 8 Mbyte until detected */
348 #define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BR_BA_MSK) | BR_V )
350 /* BCSRx - Board Control and Status Registers */
351 #define CFG_OR1_PRELIM 0xFFFF8110 /* 64Kbyte address space */
352 #define CFG_BR1_PRELIM ((BCSR_ADDR) | BR_V)
355 * Internal Definitions
359 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
360 #define BOOTFLAG_WARM 0x02 /* Software reboot */
362 /* values according to the manual */
364 #define BCSR0 ((uint) (BCSR_ADDR + 0x00))
365 #define BCSR1 ((uint) (BCSR_ADDR + 0x04))
366 #define BCSR2 ((uint) (BCSR_ADDR + 0x08))
367 #define BCSR3 ((uint) (BCSR_ADDR + 0x0c))
368 #define BCSR4 ((uint) (BCSR_ADDR + 0x10))
371 * (F)ADS bitvalues by Helmut Buchsbaum
373 * See User's Manual for a proper
374 * description of the following structures
377 #define BCSR0_ERB ((uint)0x80000000)
378 #define BCSR0_IP ((uint)0x40000000)
379 #define BCSR0_BDIS ((uint)0x10000000)
380 #define BCSR0_BPS_MASK ((uint)0x0C000000)
381 #define BCSR0_ISB_MASK ((uint)0x01800000)
382 #define BCSR0_DBGC_MASK ((uint)0x00600000)
383 #define BCSR0_DBPC_MASK ((uint)0x00180000)
384 #define BCSR0_EBDF_MASK ((uint)0x00060000)
386 #define BCSR1_FLASH_EN ((uint)0x80000000)
387 #define BCSR1_DRAM_EN ((uint)0x40000000)
388 #define BCSR1_ETHEN ((uint)0x20000000)
389 #define BCSR1_IRDEN ((uint)0x10000000)
390 #define BCSR1_FLASH_CFG_EN ((uint)0x08000000)
391 #define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
392 #define BCSR1_BCSR_EN ((uint)0x02000000)
393 #define BCSR1_RS232EN_1 ((uint)0x01000000)
394 #define BCSR1_PCCEN ((uint)0x00800000)
395 #define BCSR1_PCCVCC0 ((uint)0x00400000)
396 #define BCSR1_PCCVPP_MASK ((uint)0x00300000)
397 #define BCSR1_DRAM_HALF_WORD ((uint)0x00080000)
398 #define BCSR1_RS232EN_2 ((uint)0x00040000)
399 #define BCSR1_SDRAM_EN ((uint)0x00020000)
400 #define BCSR1_PCCVCC1 ((uint)0x00010000)
402 #define BCSR1_PCCVCCON BCSR1_PCCVCC0
404 #define BCSR2_FLASH_PD_MASK ((uint)0xF0000000)
405 #define BCSR2_FLASH_PD_SHIFT 28
406 #define BCSR2_DRAM_PD_MASK ((uint)0x07800000)
407 #define BCSR2_DRAM_PD_SHIFT 23
408 #define BCSR2_EXTTOLI_MASK ((uint)0x00780000)
409 #define BCSR2_DBREVNR_MASK ((uint)0x00030000)
411 #define BCSR3_DBID_MASK ((ushort)0x3800)
412 #define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
413 #define BCSR3_BREVNR0 ((ushort)0x0080)
414 #define BCSR3_FLASH_PD_MASK ((ushort)0x0070)
415 #define BCSR3_BREVN1 ((ushort)0x0008)
416 #define BCSR3_BREVN2_MASK ((ushort)0x0003)
418 #define BCSR4_ETHLOOP ((uint)0x80000000)
419 #define BCSR4_TFPLDL ((uint)0x40000000)
420 #define BCSR4_TPSQEL ((uint)0x20000000)
421 #define BCSR4_SIGNAL_LAMP ((uint)0x10000000)
422 #if defined(CONFIG_MPC823)
423 #define BCSR4_USB_EN ((uint)0x08000000)
424 #define BCSR4_USB_SPEED ((uint)0x04000000)
425 #define BCSR4_VCCO ((uint)0x02000000)
426 #define BCSR4_VIDEO_ON ((uint)0x00800000)
427 #define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000)
428 #define BCSR4_VIDEO_RST ((uint)0x00200000)
429 #define BCSR4_MODEM_EN ((uint)0x00100000)
430 #define BCSR4_DATA_VOICE ((uint)0x00080000)
431 #elif defined(CONFIG_MPC850)
432 #define BCSR4_DATA_VOICE ((uint)0x00080000)
433 #elif defined(CONFIG_MPC860SAR)
434 #define BCSR4_UTOPIA_EN ((uint)0x08000000)
435 #else /* MPC860T and other chips with FEC */
436 #define BCSR4_FETH_EN ((uint)0x08000000)
437 #define BCSR4_FETHCFG0 ((uint)0x04000000)
438 #define BCSR4_FETHFDE ((uint)0x02000000)
439 #define BCSR4_FETHCFG1 ((uint)0x00400000)
440 #define BCSR4_FETHRST ((uint)0x00200000)
443 /* BSCR5 exists on MPC86xADS and MPC885ADS only */
445 #define CFG_PHYDEV_ADDR (BCSR_ADDR + 0x20000)
447 #define BCSR5 (CFG_PHYDEV_ADDR + 0x300)
449 #define BCSR5_MII2_EN 0x40
450 #define BCSR5_MII2_RST 0x20
451 #define BCSR5_T1_RST 0x10
452 #define BCSR5_ATM155_RST 0x08
453 #define BCSR5_ATM25_RST 0x04
454 #define BCSR5_MII1_EN 0x02
455 #define BCSR5_MII1_RST 0x01
457 /* We don't use the 8259.
459 #define NR_8259_INTS 0
461 /*-----------------------------------------------------------------------
463 *-----------------------------------------------------------------------
465 #define CFG_PCMCIA_MEM_ADDR (0xE0000000)
466 #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
467 #define CFG_PCMCIA_DMA_ADDR (0xE4000000)
468 #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
469 #define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
470 #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
471 #define CFG_PCMCIA_IO_ADDR (0xEC000000)
472 #define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
474 /*-----------------------------------------------------------------------
476 *-----------------------------------------------------------------------
478 #define CONFIG_MAC_PARTITION 1
479 #define CONFIG_DOS_PARTITION 1
480 #define CONFIG_ISO_PARTITION 1
483 #if 0 /* does not make sense when CONFIG_CMD_IDE is not enabled, too */
484 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
486 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
487 #undef CONFIG_IDE_LED /* LED for ide not supported */
488 #undef CONFIG_IDE_RESET /* reset for ide not supported */
490 #define CFG_IDE_MAXBUS 1 /* max. 2 IDE busses */
491 #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
493 #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
494 #define CFG_ATA_IDE0_OFFSET 0x0000
496 /* Offset for data I/O */
497 #define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
498 /* Offset for normal register accesses */
499 #define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
500 /* Offset for alternate registers */
501 #define CFG_ATA_ALT_OFFSET 0x0000
503 #define CONFIG_DISK_SPINUP_TIME 1000000
504 /* #undef CONFIG_DISK_SPINUP_TIME */ /* usin Compact Flash */