2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Derived from FADS860T definitions by Magnus Damm, Helmut Buchsbaum,
8 * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
10 * This header file contains values common to all FADS family boards.
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 /****************************************************************************
32 * Flash Memory Map as used by U-Boot:
34 * Start Address Length
35 * +-----------------------+ 0xFE00_0000 Start of Flash -----------------
36 * | | 0xFE00_0100 Reset Vector
40 * +-----------------------+ 0xFE04_0000 (sector border)
43 * | U-Boot environment |
46 * +=======================+ 0xFE08_0000 (sector border) -----------------
47 * | Available | | Applications
50 *****************************************************************************/
53 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
55 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
58 #define CONFIG_ENV_OVERWRITE
60 #define CONFIG_NFSBOOTCOMMAND \
62 "setenv bootargs root=/dev/nfs rw nfsroot=$rootpath " \
63 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
66 #define CONFIG_BOOTCOMMAND \
67 "setenv bootargs root=/dev/mtdblock2 rw mtdparts=phys:1280K(ROM)ro,-(root) "\
68 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
71 #undef CONFIG_BOOTARGS
73 #undef CONFIG_WATCHDOG /* watchdog disabled */
75 #if !defined(CONFIG_MPC885ADS)
76 #define CONFIG_BZIP2 /* include support for bzip2 compressed images */
80 * New MPC86xADS and MPC885ADS provide two Ethernet connectivity options:
81 * 10Mbit/s on SCC and 100Mbit/s on FEC. FADS provides SCC Ethernet on
82 * motherboard and FEC Ethernet on daughterboard. All new PQ1 chips have
83 * got FEC so FEC is the default.
86 #undef CONFIG_SCC1_ENET /* Disable SCC1 ethernet */
87 #define CONFIG_FEC_ENET /* Use FEC ethernet */
88 #else /* Old ADS has not got FEC option */
89 #define CONFIG_SCC1_ENET /* Use SCC1 ethernet */
90 #undef CONFIG_FEC_ENET /* No FEC ethernet */
91 #endif /* !CONFIG_ADS */
93 #if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
94 #error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
97 #ifdef CONFIG_FEC_ENET
98 #define CONFIG_SYS_DISCOVER_PHY
99 #define CONFIG_MII_INIT 1
106 #define CONFIG_BOOTP_BOOTFILESIZE
107 #define CONFIG_BOOTP_BOOTPATH
108 #define CONFIG_BOOTP_GATEWAY
109 #define CONFIG_BOOTP_HOSTNAME
112 #if !defined(FADS_COMMANDS_ALREADY_DEFINED)
114 * Command line configuration.
116 #include <config_cmd_default.h>
118 #define CONFIG_CMD_ASKENV
119 #define CONFIG_CMD_DHCP
120 #define CONFIG_CMD_ECHO
121 #define CONFIG_CMD_IMMAP
122 #define CONFIG_CMD_JFFS2
123 #define CONFIG_CMD_MII
124 #define CONFIG_CMD_PCMCIA
125 #define CONFIG_CMD_PING
131 * Miscellaneous configurable options
133 #define CONFIG_SYS_PROMPT "=>" /* Monitor Command Prompt */
134 #define CONFIG_SYS_HUSH_PARSER
135 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
136 #define CONFIG_SYS_LONGHELP /* #undef to save memory */
137 #if defined(CONFIG_CMD_KGDB)
138 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
140 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
142 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
143 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
144 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
146 #define CONFIG_SYS_LOAD_ADDR 0x00100000
148 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
151 * Low Level Configuration Settings
152 * (address mappings, register initial values, etc.)
153 * You should know what you are doing if you make changes here.
156 /*-----------------------------------------------------------------------
157 * Internal Memory Mapped Register
159 #define CONFIG_SYS_IMMR 0xFF000000
161 /*-----------------------------------------------------------------------
162 * Definitions for initial stack pointer and data area (in DPRAM)
164 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
165 #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
166 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
167 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
169 /*-----------------------------------------------------------------------
170 * Start addresses for the final memory configuration
171 * (Set up by the startup code)
172 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
174 #define CONFIG_SYS_SDRAM_BASE 0x00000000
175 #if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC885ADS) /* New ADS or Duet */
176 #define CONFIG_SYS_SDRAM_SIZE 0x00800000 /* 8 Mbyte */
179 * 1000 factor s -> ms
180 * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
181 * 4 Number of refresh cycles per period
182 * 64 Refresh cycle in ms per number of rows
184 #define CONFIG_SYS_PTA_PER_CLK ((2048 * 64 * 1000) / (4 * 64))
185 #elif defined(CONFIG_FADS) /* Old/new FADS */
186 #define CONFIG_SYS_SDRAM_SIZE 0x00400000 /* 4 Mbyte */
188 #define CONFIG_SYS_SDRAM_SIZE 0x00000000 /* No SDRAM */
191 #define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
192 #if (CONFIG_SYS_SDRAM_SIZE)
193 #define CONFIG_SYS_MEMTEST_END CONFIG_SYS_SDRAM_SIZE /* 1 ... SDRAM_SIZE */
195 #define CONFIG_SYS_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
196 #endif /* CONFIG_SYS_SDRAM_SIZE */
199 * For booting Linux, the board info and command line data
200 * have to be in the first 8 MB of memory, since this is
201 * the maximum mapped by the Linux kernel during initialization.
203 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
205 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
206 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 KB for monitor */
209 #define CONFIG_SYS_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */
211 #define CONFIG_SYS_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */
212 #endif /* CONFIG_BZIP2 */
214 /*-----------------------------------------------------------------------
217 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
218 #define CONFIG_SYS_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
220 #define CONFIG_SYS_MAX_FLASH_BANKS 4 /* max number of memory banks */
221 #define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
223 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
224 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
226 #define CONFIG_ENV_IS_IN_FLASH 1
227 #define CONFIG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */
228 #define CONFIG_ENV_OFFSET CONFIG_ENV_SECT_SIZE
229 #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment */
230 #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
232 #define CONFIG_SYS_DIRECT_FLASH_TFTP
234 #if defined(CONFIG_CMD_JFFS2)
240 /* No command line, one static partition, whole device */
241 #undef CONFIG_CMD_MTDPARTS
242 #define CONFIG_JFFS2_DEV "nor0"
243 #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
244 #define CONFIG_JFFS2_PART_OFFSET 0x00000000
246 /* mtdparts command line support */
247 /* Note: fake mtd_id used, no linux mtd map file */
249 #define CONFIG_CMD_MTDPARTS
250 #define MTDIDS_DEFAULT "nor0=fads0,nor1=fads-1,nor2=fads-2,nor3=fads-3"
251 #define MTDPARTS_DEFAULT "mtdparts=fads-0:-@1m(user1),fads-1:-(user2),fads-2:-(user3),fads-3:-(user4)"
254 #define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
257 /*-----------------------------------------------------------------------
258 * Cache Configuration
260 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
261 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
263 /*-----------------------------------------------------------------------
266 #if defined(CONFIG_CMD_I2C)
267 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
268 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address defaults */
269 #define CONFIG_SYS_I2C_SLAVE 0x7F
272 /*-----------------------------------------------------------------------
273 * SYPCR - System Protection Control 11-9
274 * SYPCR can only be written once after reset!
275 *-----------------------------------------------------------------------
276 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
278 #if defined(CONFIG_WATCHDOG)
279 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
280 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
282 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
285 /*-----------------------------------------------------------------------
286 * SIUMCR - SIU Module Configuration 11-6
287 *-----------------------------------------------------------------------
288 * PCMCIA config., multi-function pin tri-state
290 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
292 /*-----------------------------------------------------------------------
293 * TBSCR - Time Base Status and Control 11-26
294 *-----------------------------------------------------------------------
295 * Clear Reference Interrupt Status, Timebase freezing enabled
297 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
299 /*-----------------------------------------------------------------------
300 * PISCR - Periodic Interrupt Status and Control 11-31
301 *-----------------------------------------------------------------------
302 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
304 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
306 /*-----------------------------------------------------------------------
307 * SCCR - System Clock and reset Control Register 15-27
308 *-----------------------------------------------------------------------
309 * Set clock output, timebase and RTC source and divider,
310 * power management and some other internal clocks
312 #define SCCR_MASK SCCR_EBDF11
313 #define CONFIG_SYS_SCCR SCCR_TBS
315 /*-----------------------------------------------------------------------
316 * DER - Debug Enable Register
317 *-----------------------------------------------------------------------
318 * Set to zero to prevent the processor from entering debug mode
320 #define CONFIG_SYS_DER 0
322 /* Because of the way the 860 starts up and assigns CS0 the entire
323 * address space, we have to set the memory controller differently.
324 * Normally, you write the option register first, and then enable the
325 * chip select by writing the base register. For CS0, you must write
326 * the base register first, followed by the option register.
330 * Init Memory Controller:
335 /* the other CS:s are determined by looking at parameters in BCSRx */
337 #define BCSR_ADDR ((uint) 0xFF080000)
339 #define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
341 /* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
342 #define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
344 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) /* 8 Mbyte until detected */
345 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_V )
347 /* BCSRx - Board Control and Status Registers */
348 #define CONFIG_SYS_OR1_PRELIM 0xFFFF8110 /* 64Kbyte address space */
349 #define CONFIG_SYS_BR1_PRELIM ((BCSR_ADDR) | BR_V)
351 /* values according to the manual */
353 #define BCSR0 ((uint) (BCSR_ADDR + 0x00))
354 #define BCSR1 ((uint) (BCSR_ADDR + 0x04))
355 #define BCSR2 ((uint) (BCSR_ADDR + 0x08))
356 #define BCSR3 ((uint) (BCSR_ADDR + 0x0c))
357 #define BCSR4 ((uint) (BCSR_ADDR + 0x10))
360 * (F)ADS bitvalues by Helmut Buchsbaum
362 * See User's Manual for a proper
363 * description of the following structures
366 #define BCSR0_ERB ((uint)0x80000000)
367 #define BCSR0_IP ((uint)0x40000000)
368 #define BCSR0_BDIS ((uint)0x10000000)
369 #define BCSR0_BPS_MASK ((uint)0x0C000000)
370 #define BCSR0_ISB_MASK ((uint)0x01800000)
371 #define BCSR0_DBGC_MASK ((uint)0x00600000)
372 #define BCSR0_DBPC_MASK ((uint)0x00180000)
373 #define BCSR0_EBDF_MASK ((uint)0x00060000)
375 #define BCSR1_FLASH_EN ((uint)0x80000000)
376 #define BCSR1_DRAM_EN ((uint)0x40000000)
377 #define BCSR1_ETHEN ((uint)0x20000000)
378 #define BCSR1_IRDEN ((uint)0x10000000)
379 #define BCSR1_FLASH_CFG_EN ((uint)0x08000000)
380 #define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
381 #define BCSR1_BCSR_EN ((uint)0x02000000)
382 #define BCSR1_RS232EN_1 ((uint)0x01000000)
383 #define BCSR1_PCCEN ((uint)0x00800000)
384 #define BCSR1_PCCVCC0 ((uint)0x00400000)
385 #define BCSR1_PCCVPP_MASK ((uint)0x00300000)
386 #define BCSR1_DRAM_HALF_WORD ((uint)0x00080000)
387 #define BCSR1_RS232EN_2 ((uint)0x00040000)
388 #define BCSR1_SDRAM_EN ((uint)0x00020000)
389 #define BCSR1_PCCVCC1 ((uint)0x00010000)
391 #define BCSR1_PCCVCCON BCSR1_PCCVCC0
393 #define BCSR2_FLASH_PD_MASK ((uint)0xF0000000)
394 #define BCSR2_FLASH_PD_SHIFT 28
395 #define BCSR2_DRAM_PD_MASK ((uint)0x07800000)
396 #define BCSR2_DRAM_PD_SHIFT 23
397 #define BCSR2_EXTTOLI_MASK ((uint)0x00780000)
398 #define BCSR2_DBREVNR_MASK ((uint)0x00030000)
400 #define BCSR3_DBID_MASK ((ushort)0x3800)
401 #define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
402 #define BCSR3_BREVNR0 ((ushort)0x0080)
403 #define BCSR3_FLASH_PD_MASK ((ushort)0x0070)
404 #define BCSR3_BREVN1 ((ushort)0x0008)
405 #define BCSR3_BREVN2_MASK ((ushort)0x0003)
407 #define BCSR4_ETHLOOP ((uint)0x80000000)
408 #define BCSR4_TFPLDL ((uint)0x40000000)
409 #define BCSR4_TPSQEL ((uint)0x20000000)
410 #define BCSR4_SIGNAL_LAMP ((uint)0x10000000)
411 #if defined(CONFIG_MPC823)
412 #define BCSR4_USB_EN ((uint)0x08000000)
413 #define BCSR4_USB_SPEED ((uint)0x04000000)
414 #define BCSR4_VCCO ((uint)0x02000000)
415 #define BCSR4_VIDEO_ON ((uint)0x00800000)
416 #define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000)
417 #define BCSR4_VIDEO_RST ((uint)0x00200000)
418 #define BCSR4_MODEM_EN ((uint)0x00100000)
419 #define BCSR4_DATA_VOICE ((uint)0x00080000)
420 #elif defined(CONFIG_MPC850)
421 #define BCSR4_DATA_VOICE ((uint)0x00080000)
422 #elif defined(CONFIG_MPC860SAR)
423 #define BCSR4_UTOPIA_EN ((uint)0x08000000)
424 #else /* MPC860T and other chips with FEC */
425 #define BCSR4_FETH_EN ((uint)0x08000000)
426 #define BCSR4_FETHCFG0 ((uint)0x04000000)
427 #define BCSR4_FETHFDE ((uint)0x02000000)
428 #define BCSR4_FETHCFG1 ((uint)0x00400000)
429 #define BCSR4_FETHRST ((uint)0x00200000)
432 /* BSCR5 exists on MPC86xADS and MPC885ADS only */
434 #define CONFIG_SYS_PHYDEV_ADDR (BCSR_ADDR + 0x20000)
436 #define BCSR5 (CONFIG_SYS_PHYDEV_ADDR + 0x300)
438 #define BCSR5_MII2_EN 0x40
439 #define BCSR5_MII2_RST 0x20
440 #define BCSR5_T1_RST 0x10
441 #define BCSR5_ATM155_RST 0x08
442 #define BCSR5_ATM25_RST 0x04
443 #define BCSR5_MII1_EN 0x02
444 #define BCSR5_MII1_RST 0x01
446 /* We don't use the 8259.
448 #define NR_8259_INTS 0
450 /*-----------------------------------------------------------------------
452 *-----------------------------------------------------------------------
454 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
455 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
456 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
457 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
458 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
459 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
460 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
461 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
463 /*-----------------------------------------------------------------------
465 *-----------------------------------------------------------------------
467 #define CONFIG_MAC_PARTITION 1
468 #define CONFIG_DOS_PARTITION 1
469 #define CONFIG_ISO_PARTITION 1
472 #if 0 /* does not make sense when CONFIG_CMD_IDE is not enabled, too */
473 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
475 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
476 #undef CONFIG_IDE_LED /* LED for ide not supported */
477 #undef CONFIG_IDE_RESET /* reset for ide not supported */
479 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 2 IDE busses */
480 #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
482 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
483 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
485 /* Offset for data I/O */
486 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
487 /* Offset for normal register accesses */
488 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
489 /* Offset for alternate registers */
490 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0000
492 #define CONFIG_DISK_SPINUP_TIME 1000000
493 /* #undef CONFIG_DISK_SPINUP_TIME */ /* usin Compact Flash */