2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Derived from FADS860T definitions by Magnus Damm, Helmut Buchsbaum,
8 * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
10 * This header file contains values common to all FADS family boards.
12 * SPDX-License-Identifier: GPL-2.0+
15 /****************************************************************************
16 * Flash Memory Map as used by U-Boot:
18 * Start Address Length
19 * +-----------------------+ 0xFE00_0000 Start of Flash -----------------
20 * | | 0xFE00_0100 Reset Vector
24 * +-----------------------+ 0xFE04_0000 (sector border)
27 * | U-Boot environment |
30 * +=======================+ 0xFE08_0000 (sector border) -----------------
31 * | Available | | Applications
34 *****************************************************************************/
37 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
39 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
42 #define CONFIG_ENV_OVERWRITE
44 #define CONFIG_NFSBOOTCOMMAND \
46 "setenv bootargs root=/dev/nfs rw nfsroot=$rootpath " \
47 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
50 #define CONFIG_BOOTCOMMAND \
51 "setenv bootargs root=/dev/mtdblock2 rw mtdparts=phys:1280K(ROM)ro,-(root) "\
52 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
55 #undef CONFIG_BOOTARGS
57 #undef CONFIG_WATCHDOG /* watchdog disabled */
59 #if !defined(CONFIG_MPC885ADS)
60 #define CONFIG_BZIP2 /* include support for bzip2 compressed images */
64 * New MPC86xADS and MPC885ADS provide two Ethernet connectivity options:
65 * 10Mbit/s on SCC and 100Mbit/s on FEC. FADS provides SCC Ethernet on
66 * motherboard and FEC Ethernet on daughterboard. All new PQ1 chips have
67 * got FEC so FEC is the default.
70 #undef CONFIG_SCC1_ENET /* Disable SCC1 ethernet */
71 #define CONFIG_FEC_ENET /* Use FEC ethernet */
72 #else /* Old ADS has not got FEC option */
73 #define CONFIG_SCC1_ENET /* Use SCC1 ethernet */
74 #undef CONFIG_FEC_ENET /* No FEC ethernet */
75 #endif /* !CONFIG_ADS */
77 #if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
78 #error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
81 #ifdef CONFIG_FEC_ENET
82 #define CONFIG_SYS_DISCOVER_PHY
83 #define CONFIG_MII_INIT 1
90 #define CONFIG_BOOTP_BOOTFILESIZE
91 #define CONFIG_BOOTP_BOOTPATH
92 #define CONFIG_BOOTP_GATEWAY
93 #define CONFIG_BOOTP_HOSTNAME
96 #if !defined(FADS_COMMANDS_ALREADY_DEFINED)
98 * Command line configuration.
100 #include <config_cmd_default.h>
102 #define CONFIG_CMD_ASKENV
103 #define CONFIG_CMD_DHCP
104 #define CONFIG_CMD_ECHO
105 #define CONFIG_CMD_IMMAP
106 #define CONFIG_CMD_JFFS2
107 #define CONFIG_CMD_MII
108 #define CONFIG_CMD_PCMCIA
109 #define CONFIG_CMD_PING
115 * Miscellaneous configurable options
117 #define CONFIG_SYS_PROMPT "=>" /* Monitor Command Prompt */
118 #define CONFIG_SYS_HUSH_PARSER
119 #define CONFIG_SYS_LONGHELP /* #undef to save memory */
120 #if defined(CONFIG_CMD_KGDB)
121 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
123 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
125 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
126 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
127 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
129 #define CONFIG_SYS_LOAD_ADDR 0x00100000
131 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
134 * Low Level Configuration Settings
135 * (address mappings, register initial values, etc.)
136 * You should know what you are doing if you make changes here.
139 /*-----------------------------------------------------------------------
140 * Internal Memory Mapped Register
142 #define CONFIG_SYS_IMMR 0xFF000000
144 /*-----------------------------------------------------------------------
145 * Definitions for initial stack pointer and data area (in DPRAM)
147 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
148 #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
149 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
150 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
152 /*-----------------------------------------------------------------------
153 * Start addresses for the final memory configuration
154 * (Set up by the startup code)
155 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
157 #define CONFIG_SYS_SDRAM_BASE 0x00000000
158 #if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC885ADS) /* New ADS or Duet */
159 #define CONFIG_SYS_SDRAM_SIZE 0x00800000 /* 8 Mbyte */
162 * 1000 factor s -> ms
163 * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
164 * 4 Number of refresh cycles per period
165 * 64 Refresh cycle in ms per number of rows
167 #define CONFIG_SYS_PTA_PER_CLK ((2048 * 64 * 1000) / (4 * 64))
168 #elif defined(CONFIG_FADS) /* Old/new FADS */
169 #define CONFIG_SYS_SDRAM_SIZE 0x00400000 /* 4 Mbyte */
171 #define CONFIG_SYS_SDRAM_SIZE 0x00000000 /* No SDRAM */
174 #define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
175 #if (CONFIG_SYS_SDRAM_SIZE)
176 #define CONFIG_SYS_MEMTEST_END CONFIG_SYS_SDRAM_SIZE /* 1 ... SDRAM_SIZE */
178 #define CONFIG_SYS_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
179 #endif /* CONFIG_SYS_SDRAM_SIZE */
182 * For booting Linux, the board info and command line data
183 * have to be in the first 8 MB of memory, since this is
184 * the maximum mapped by the Linux kernel during initialization.
186 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
188 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
189 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 KB for monitor */
192 #define CONFIG_SYS_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */
194 #define CONFIG_SYS_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */
195 #endif /* CONFIG_BZIP2 */
197 /*-----------------------------------------------------------------------
200 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
201 #define CONFIG_SYS_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
203 #define CONFIG_SYS_MAX_FLASH_BANKS 4 /* max number of memory banks */
204 #define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
206 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
207 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
209 #define CONFIG_ENV_IS_IN_FLASH 1
210 #define CONFIG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */
211 #define CONFIG_ENV_OFFSET CONFIG_ENV_SECT_SIZE
212 #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment */
213 #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
215 #define CONFIG_SYS_DIRECT_FLASH_TFTP
217 #if defined(CONFIG_CMD_JFFS2)
223 /* No command line, one static partition, whole device */
224 #undef CONFIG_CMD_MTDPARTS
225 #define CONFIG_JFFS2_DEV "nor0"
226 #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
227 #define CONFIG_JFFS2_PART_OFFSET 0x00000000
229 /* mtdparts command line support */
230 /* Note: fake mtd_id used, no linux mtd map file */
232 #define CONFIG_CMD_MTDPARTS
233 #define MTDIDS_DEFAULT "nor0=fads0,nor1=fads-1,nor2=fads-2,nor3=fads-3"
234 #define MTDPARTS_DEFAULT "mtdparts=fads-0:-@1m(user1),fads-1:-(user2),fads-2:-(user3),fads-3:-(user4)"
237 #define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
240 /*-----------------------------------------------------------------------
241 * Cache Configuration
243 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
244 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
246 /*-----------------------------------------------------------------------
249 #if defined(CONFIG_CMD_I2C)
250 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
251 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address defaults */
252 #define CONFIG_SYS_I2C_SLAVE 0x7F
255 /*-----------------------------------------------------------------------
256 * SYPCR - System Protection Control 11-9
257 * SYPCR can only be written once after reset!
258 *-----------------------------------------------------------------------
259 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
261 #if defined(CONFIG_WATCHDOG)
262 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
263 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
265 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
268 /*-----------------------------------------------------------------------
269 * SIUMCR - SIU Module Configuration 11-6
270 *-----------------------------------------------------------------------
271 * PCMCIA config., multi-function pin tri-state
273 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
275 /*-----------------------------------------------------------------------
276 * TBSCR - Time Base Status and Control 11-26
277 *-----------------------------------------------------------------------
278 * Clear Reference Interrupt Status, Timebase freezing enabled
280 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
282 /*-----------------------------------------------------------------------
283 * PISCR - Periodic Interrupt Status and Control 11-31
284 *-----------------------------------------------------------------------
285 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
287 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
289 /*-----------------------------------------------------------------------
290 * SCCR - System Clock and reset Control Register 15-27
291 *-----------------------------------------------------------------------
292 * Set clock output, timebase and RTC source and divider,
293 * power management and some other internal clocks
295 #define SCCR_MASK SCCR_EBDF11
296 #define CONFIG_SYS_SCCR SCCR_TBS
298 /*-----------------------------------------------------------------------
299 * DER - Debug Enable Register
300 *-----------------------------------------------------------------------
301 * Set to zero to prevent the processor from entering debug mode
303 #define CONFIG_SYS_DER 0
305 /* Because of the way the 860 starts up and assigns CS0 the entire
306 * address space, we have to set the memory controller differently.
307 * Normally, you write the option register first, and then enable the
308 * chip select by writing the base register. For CS0, you must write
309 * the base register first, followed by the option register.
313 * Init Memory Controller:
318 /* the other CS:s are determined by looking at parameters in BCSRx */
320 #define BCSR_ADDR ((uint) 0xFF080000)
322 #define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
324 /* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
325 #define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
327 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) /* 8 Mbyte until detected */
328 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_V )
330 /* BCSRx - Board Control and Status Registers */
331 #define CONFIG_SYS_OR1_PRELIM 0xFFFF8110 /* 64Kbyte address space */
332 #define CONFIG_SYS_BR1_PRELIM ((BCSR_ADDR) | BR_V)
334 /* values according to the manual */
336 #define BCSR0 ((uint) (BCSR_ADDR + 0x00))
337 #define BCSR1 ((uint) (BCSR_ADDR + 0x04))
338 #define BCSR2 ((uint) (BCSR_ADDR + 0x08))
339 #define BCSR3 ((uint) (BCSR_ADDR + 0x0c))
340 #define BCSR4 ((uint) (BCSR_ADDR + 0x10))
343 * (F)ADS bitvalues by Helmut Buchsbaum
345 * See User's Manual for a proper
346 * description of the following structures
349 #define BCSR0_ERB ((uint)0x80000000)
350 #define BCSR0_IP ((uint)0x40000000)
351 #define BCSR0_BDIS ((uint)0x10000000)
352 #define BCSR0_BPS_MASK ((uint)0x0C000000)
353 #define BCSR0_ISB_MASK ((uint)0x01800000)
354 #define BCSR0_DBGC_MASK ((uint)0x00600000)
355 #define BCSR0_DBPC_MASK ((uint)0x00180000)
356 #define BCSR0_EBDF_MASK ((uint)0x00060000)
358 #define BCSR1_FLASH_EN ((uint)0x80000000)
359 #define BCSR1_DRAM_EN ((uint)0x40000000)
360 #define BCSR1_ETHEN ((uint)0x20000000)
361 #define BCSR1_IRDEN ((uint)0x10000000)
362 #define BCSR1_FLASH_CFG_EN ((uint)0x08000000)
363 #define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
364 #define BCSR1_BCSR_EN ((uint)0x02000000)
365 #define BCSR1_RS232EN_1 ((uint)0x01000000)
366 #define BCSR1_PCCEN ((uint)0x00800000)
367 #define BCSR1_PCCVCC0 ((uint)0x00400000)
368 #define BCSR1_PCCVPP_MASK ((uint)0x00300000)
369 #define BCSR1_DRAM_HALF_WORD ((uint)0x00080000)
370 #define BCSR1_RS232EN_2 ((uint)0x00040000)
371 #define BCSR1_SDRAM_EN ((uint)0x00020000)
372 #define BCSR1_PCCVCC1 ((uint)0x00010000)
374 #define BCSR1_PCCVCCON BCSR1_PCCVCC0
376 #define BCSR2_FLASH_PD_MASK ((uint)0xF0000000)
377 #define BCSR2_FLASH_PD_SHIFT 28
378 #define BCSR2_DRAM_PD_MASK ((uint)0x07800000)
379 #define BCSR2_DRAM_PD_SHIFT 23
380 #define BCSR2_EXTTOLI_MASK ((uint)0x00780000)
381 #define BCSR2_DBREVNR_MASK ((uint)0x00030000)
383 #define BCSR3_DBID_MASK ((ushort)0x3800)
384 #define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
385 #define BCSR3_BREVNR0 ((ushort)0x0080)
386 #define BCSR3_FLASH_PD_MASK ((ushort)0x0070)
387 #define BCSR3_BREVN1 ((ushort)0x0008)
388 #define BCSR3_BREVN2_MASK ((ushort)0x0003)
390 #define BCSR4_ETHLOOP ((uint)0x80000000)
391 #define BCSR4_TFPLDL ((uint)0x40000000)
392 #define BCSR4_TPSQEL ((uint)0x20000000)
393 #define BCSR4_SIGNAL_LAMP ((uint)0x10000000)
394 #if defined(CONFIG_MPC823)
395 #define BCSR4_USB_EN ((uint)0x08000000)
396 #define BCSR4_USB_SPEED ((uint)0x04000000)
397 #define BCSR4_VCCO ((uint)0x02000000)
398 #define BCSR4_VIDEO_ON ((uint)0x00800000)
399 #define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000)
400 #define BCSR4_VIDEO_RST ((uint)0x00200000)
401 #define BCSR4_MODEM_EN ((uint)0x00100000)
402 #define BCSR4_DATA_VOICE ((uint)0x00080000)
403 #elif defined(CONFIG_MPC850)
404 #define BCSR4_DATA_VOICE ((uint)0x00080000)
405 #elif defined(CONFIG_MPC860SAR)
406 #define BCSR4_UTOPIA_EN ((uint)0x08000000)
407 #else /* MPC860T and other chips with FEC */
408 #define BCSR4_FETH_EN ((uint)0x08000000)
409 #define BCSR4_FETHCFG0 ((uint)0x04000000)
410 #define BCSR4_FETHFDE ((uint)0x02000000)
411 #define BCSR4_FETHCFG1 ((uint)0x00400000)
412 #define BCSR4_FETHRST ((uint)0x00200000)
415 /* BSCR5 exists on MPC86xADS and MPC885ADS only */
417 #define CONFIG_SYS_PHYDEV_ADDR (BCSR_ADDR + 0x20000)
419 #define BCSR5 (CONFIG_SYS_PHYDEV_ADDR + 0x300)
421 #define BCSR5_MII2_EN 0x40
422 #define BCSR5_MII2_RST 0x20
423 #define BCSR5_T1_RST 0x10
424 #define BCSR5_ATM155_RST 0x08
425 #define BCSR5_ATM25_RST 0x04
426 #define BCSR5_MII1_EN 0x02
427 #define BCSR5_MII1_RST 0x01
429 /* We don't use the 8259.
431 #define NR_8259_INTS 0
433 /*-----------------------------------------------------------------------
435 *-----------------------------------------------------------------------
437 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
438 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
439 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
440 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
441 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
442 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
443 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
444 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
446 /*-----------------------------------------------------------------------
448 *-----------------------------------------------------------------------
450 #define CONFIG_MAC_PARTITION 1
451 #define CONFIG_DOS_PARTITION 1
452 #define CONFIG_ISO_PARTITION 1
455 #if 0 /* does not make sense when CONFIG_CMD_IDE is not enabled, too */
456 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
458 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
459 #undef CONFIG_IDE_LED /* LED for ide not supported */
460 #undef CONFIG_IDE_RESET /* reset for ide not supported */
462 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 2 IDE busses */
463 #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
465 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
466 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
468 /* Offset for data I/O */
469 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
470 /* Offset for normal register accesses */
471 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
472 /* Offset for alternate registers */
473 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0000
475 #define CONFIG_DISK_SPINUP_TIME 1000000
476 /* #undef CONFIG_DISK_SPINUP_TIME */ /* usin Compact Flash */