board/evb64260/eth.c

   1 /**************************************************************************
   2 Etherboot -  BOOTP/TFTP Bootstrap Program
   3 Skeleton NIC driver for Etherboot
   4 ***************************************************************************/
   5
   6 /*
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2, or (at
  10  * your option) any later version.
  11  */
  12
  13 /*
  14  * This file is a modified version from the Galileo polled mode
  15  * network driver for the ethernet contained within the GT64260
  16  * chip. It has been modified to fit into the U-Boot framework, from
  17  * the original (etherboot) setup.  Also, additional cleanup and features
  18  * were added.
  19  *
  20  * - Josh Huber <huber@mclx.com>
  21  */
  22
  23 #include <common.h>
  24 #include <malloc.h>
  25 #include <galileo/gt64260R.h>
  26 #include <galileo/core.h>
  27 #include <asm/cache.h>
  28 #include <miiphy.h>
  29 #include <net.h>
  30
  31 #include "eth.h"
  32 #include "eth_addrtbl.h"
  33
  34 #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI)
  35
  36 #define GT6426x_ETH_BUF_SIZE    1536
  37
  38 /* if you like verbose output, turn this on! */
  39 #undef DEBUG
  40
  41 /* Restart autoneg if we detect link is up on phy init. */
  42
  43 /*
  44  * The GT doc's say that after Rst is deasserted, and the PHY
  45  * reports autoneg complete, it runs through its autoneg
  46  * procedures. This doesn't seem to be the case for MII
  47  * PHY's. To work around this check for link up && autoneg
  48  * complete when initilizing the port. If they are both set,
  49  * then restart PHY autoneg. Of course, it may be something
  50  * completly different.
  51  */
  52 #ifdef CONFIG_ETHER_PORT_MII
  53 # define RESTART_AUTONEG
  54 #endif
  55
  56 /* do this if you dont want to use snooping */
  57 #define USE_SOFTWARE_CACHE_MANAGEMENT
  58
  59 #ifdef USE_SOFTWARE_CACHE_MANAGEMENT
  60 #define FLUSH_DCACHE(a,b)                if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
  61 #define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));}
  62 #define INVALIDATE_DCACHE(a,b)           if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));}
  63 #else
  64 /* bummer - w/o flush, nothing works, even with snooping - FIXME */
  65 /* #define FLUSH_DCACHE(a,b) */
  66 #define FLUSH_DCACHE(a,b)                if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
  67 #define FLUSH_AND_INVALIDATE_DCACHE(a,b)
  68 #define INVALIDATE_DCACHE(a,b)
  69 #endif
  70 struct eth_dev_s {
  71         eth0_tx_desc_single *eth_tx_desc;
  72         eth0_rx_desc_single *eth_rx_desc;
  73         char *eth_tx_buffer;
  74         char *eth_rx_buffer[NR];
  75         int tdn, rdn;
  76         int dev;
  77         unsigned int reg_base;
  78 };
  79
  80
  81 #ifdef CONFIG_INTEL_LXT97X
  82 /* for intel LXT972 */
  83 static const char ether_port_phy_addr[3]={0,1,2};
  84 #else
  85 static const char ether_port_phy_addr[3]={4,5,6};
  86 #endif
  87
  88
  89 static inline unsigned short
  90 miiphy_read_ret(unsigned short phy, unsigned short reg)
  91 {
  92     unsigned short val;
  93     miiphy_read(phy,reg,&val);
  94     return val;
  95 }
  96
  97
  98 /**************************************************************************
  99 RESET - Reset adapter
 100 ***************************************************************************/
 101 void
 102 gt6426x_eth_reset(void *v)
 103 {
 104         /*  we should do something here...
 105         struct eth_device *wp = (struct eth_device *)v;
 106         struct eth_dev_s *p = wp->priv;
 107         */
 108
 109         printf ("RESET\n");
 110         /* put the card in its initial state */
 111 }
 112
 113 static void gt6426x_handle_SMI(struct eth_dev_s *p, unsigned int icr)
 114 {
 115 #ifdef DEBUG
 116     printf("SMI interrupt: ");
 117
 118     if(icr&0x20000000) {
 119         printf("SMI done\n");
 120     }
 121 #endif
 122
 123     if(icr&0x10000000) {
 124         unsigned int psr;
 125         psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + p->reg_base);
 126 #ifdef DEBUG
 127         printf("PHY state change:\n"
 128                "  GT:%s:%s:%s:%s\n",
 129                 psr&1?"100":" 10",
 130                 psr&8?" Link":"nLink",
 131                 psr&2?"FD":"HD",
 132                 psr&4?" FC":"nFC");
 133
 134 #ifdef CONFIG_INTEL_LXT97X /* non-standard mii reg (intel lxt972a) */
 135         {
 136         unsigned short mii_11;
 137         mii_11=miiphy_read_ret(ether_port_phy_addr[p->dev],0x11);
 138
 139         printf(" mii:%s:%s:%s:%s %s:%s %s\n",
 140                 mii_11&(1<<14)?"100":" 10",
 141                 mii_11&(1<<10)?" Link":"nLink",
 142                 mii_11&(1<<9)?"FD":"HD",
 143                 mii_11&(1<<4)?" FC":"nFC",
 144
 145                 mii_11&(1<<7)?"ANc":"ANnc",
 146                 mii_11&(1<<8)?"AN":"Manual",
 147                 ""
 148                 );
 149         }
 150 #endif /* CONFIG_INTEL_LXT97X */
 151 #endif /* DEBUG */
 152     }
 153 }
 154
 155 static int
 156 gt6426x_eth_receive(struct eth_dev_s *p,unsigned int icr)
 157 {
 158         int eth_len=0;
 159         char *eth_data;
 160
 161         eth0_rx_desc_single *rx=&p->eth_rx_desc[(p->rdn)];
 162
 163         INVALIDATE_DCACHE((unsigned int)rx,(unsigned int)(rx+1));
 164
 165         if (rx->command_status & 0x80000000) {
 166                 return 0; /* No packet received */
 167         }
 168
 169         eth_len = (unsigned int)
 170                 (rx->buff_size_byte_count) & 0x0000ffff;
 171         eth_data = (char *) p->eth_rx_buffer[p->rdn];
 172
 173 #ifdef DEBUG
 174         if (eth_len) {
 175                 printf ("%s: Recived %d byte Packet @ 0x%p\n",
 176                         __FUNCTION__, eth_len, eth_data);
 177         }
 178 #endif
 179         /*
 180          * packet is now in:
 181          * eth0_rx_buffer[RDN_ETH0];
 182          */
 183
 184         /* let the upper layer handle the packet */
 185         NetReceive (eth_data, eth_len);
 186
 187         rx->buff_size_byte_count = GT6426x_ETH_BUF_SIZE<<16;
 188
 189
 190         /* GT96100 Owner */
 191         rx->command_status = 0x80000000;
 192
 193         FLUSH_DCACHE((unsigned int)rx,(unsigned int)(rx+1));
 194
 195         p->rdn ++;
 196         if (p->rdn == NR) {p->rdn = 0;}
 197
 198         sync();
 199
 200         /* Start Rx*/
 201         GT_REG_WRITE (ETHERNET0_SDMA_COMMAND_REGISTER + p->reg_base, 0x00000080);
 202
 203 #ifdef DEBUG
 204         {
 205             int i;
 206             for (i=0;i<12;i++) {
 207                 printf(" %02x", eth_data[i]);
 208             }
 209         }
 210         printf(": %d bytes\n", eth_len);
 211 #endif
 212         INVALIDATE_DCACHE((unsigned int)eth_data,
 213                 (unsigned int)eth_data+eth_len);
 214         return eth_len;
 215 }
 216
 217 /**************************************************************************
 218 POLL - look for an rx frame, handle other conditions
 219 ***************************************************************************/
 220 int
 221 gt6426x_eth_poll(void *v)
 222 {
 223         struct eth_device *wp = (struct eth_device *)v;
 224         struct eth_dev_s *p = wp->priv;
 225         unsigned int icr=GTREGREAD(ETHERNET0_INTERRUPT_CAUSE_REGISTER + p->reg_base);
 226
 227         if(icr) {
 228             GT_REG_WRITE(ETHERNET0_INTERRUPT_CAUSE_REGISTER +p->reg_base, 0);
 229 #ifdef DEBUG
 230             printf("poll got ICR %08x\n", icr);
 231 #endif
 232             /* SMI done or PHY state change*/
 233             if(icr&0x30000000) gt6426x_handle_SMI(p, icr);
 234         }
 235         /* always process. We aren't using RX interrupts */
 236         return gt6426x_eth_receive(p, icr);
 237 }
 238
 239 /**************************************************************************
 240 TRANSMIT - Transmit a frame
 241 ***************************************************************************/
 242 int
 243 gt6426x_eth_transmit(void *v, volatile char *p, unsigned int s)
 244 {
 245         struct eth_device *wp = (struct eth_device *)v;
 246         struct eth_dev_s *dev = (struct eth_dev_s *)wp->priv;
 247 #ifdef DEBUG
 248         unsigned int old_command_stat,old_psr;
 249 #endif
 250         eth0_tx_desc_single *tx=&dev->eth_tx_desc[dev->tdn];
 251
 252         /* wait for tx to be ready */
 253         INVALIDATE_DCACHE((unsigned int)tx,(unsigned int)(tx+1));
 254         while (tx->command_status & 0x80000000) {
 255             int i;
 256             for(i=0;i<1000;i++);
 257                         INVALIDATE_DCACHE((unsigned int)tx,(unsigned int)(tx+1));
 258         }
 259
 260         GT_REG_WRITE (ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 + dev->reg_base,
 261                       (unsigned int)tx);
 262
 263 #ifdef DEBUG
 264         printf("copying to tx_buffer [%p], length %x, desc = %p\n",
 265                dev->eth_tx_buffer, s, dev->eth_tx_desc);
 266 #endif
 267         memcpy(dev->eth_tx_buffer, (char *) p, s);
 268
 269         tx->buff_pointer = dev->eth_tx_buffer;
 270         tx->bytecount_reserved = ((__u16)s) << 16;
 271
 272         /*    31 - own
 273          *    22 - gencrc
 274          * 18:16 - pad, last, first */
 275         tx->command_status = (1<<31) | (1<<22) | (7<<16);
 276 #if 0
 277         /* FEr #18 */
 278         tx->next_desc = NULL;
 279 #else
 280         tx->next_desc =
 281                 (struct eth0_tx_desc_struct *)
 282                 &dev->eth_tx_desc[(dev->tdn+1)%NT].bytecount_reserved;
 283
 284         /* cpu owned */
 285         dev->eth_tx_desc[(dev->tdn+1)%NT].command_status = (7<<16);     /* pad, last, first */
 286 #endif
 287
 288 #ifdef DEBUG
 289         old_command_stat=tx->command_status,
 290         old_psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + dev->reg_base);
 291 #endif
 292
 293         FLUSH_DCACHE((unsigned int)tx,
 294                 (unsigned int)&dev->eth_tx_desc[(dev->tdn+2)%NT]);
 295
 296         FLUSH_DCACHE((unsigned int)dev->eth_tx_buffer,(unsigned int)dev->eth_tx_buffer+s);
 297
 298         GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + dev->reg_base, 0x01000000);
 299
 300 #ifdef DEBUG
 301         {
 302             unsigned int command_stat=0;
 303             printf("cmd_stat: %08x PSR: %08x\n", old_command_stat, old_psr);
 304             /* wait for tx to be ready */
 305             do {
 306                 unsigned int psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + dev->reg_base);
 307                 command_stat=tx->command_status;
 308                 if(command_stat!=old_command_stat || psr !=old_psr) {
 309                     printf("cmd_stat: %08x PSR: %08x\n", command_stat, psr);
 310                     old_command_stat = command_stat;
 311                     old_psr = psr;
 312                 }
 313                 /* gt6426x_eth0_poll(); */
 314             } while (command_stat & 0x80000000);
 315
 316             printf("sent %d byte frame\n", s);
 317
 318             if((command_stat & (3<<15)) == 3) {
 319                 printf("frame had error (stat=%08x)\n", command_stat);
 320             }
 321         }
 322 #endif
 323         return 0;
 324 }
 325
 326 /**************************************************************************
 327 DISABLE - Turn off ethernet interface
 328 ***************************************************************************/
 329 void
 330 gt6426x_eth_disable(void *v)
 331 {
 332         struct eth_device *wp = (struct eth_device *)v;
 333         struct eth_dev_s *p = (struct eth_dev_s *)wp->priv;
 334
 335         GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + p->reg_base, 0x80008000);
 336 }
 337
 338 /**************************************************************************
 339 MII utilities - write: write to an MII register via SMI
 340 ***************************************************************************/
 341 int
 342 miiphy_write(unsigned char phy, unsigned char reg,
 343     unsigned short data)
 344 {
 345     unsigned int temp= (reg<<21) | (phy<<16) | data;
 346
 347     while(GTREGREAD(ETHERNET_SMI_REGISTER) & (1<<28));  /* wait for !Busy */
 348
 349     GT_REG_WRITE(ETHERNET_SMI_REGISTER, temp);
 350     return 0;
 351 }
 352
 353 /**************************************************************************
 354 MII utilities - read: read from an MII register via SMI
 355 ***************************************************************************/
 356 int
 357 miiphy_read(unsigned char phy, unsigned char reg,
 358                         unsigned short *val)
 359 {
 360     unsigned int temp= (reg<<21) | (phy<<16) | 1<<26;
 361
 362     while(GTREGREAD(ETHERNET_SMI_REGISTER) & (1<<28));  /* wait for !Busy */
 363
 364     GT_REG_WRITE(ETHERNET_SMI_REGISTER, temp);
 365
 366     while(1) {
 367         temp=GTREGREAD(ETHERNET_SMI_REGISTER);
 368         if(temp & (1<<27)) break;               /* wait for ReadValid */
 369     }
 370     *val = temp & 0xffff;
 371
 372     return 0;
 373 }
 374
 375 #ifdef DEBUG
 376 /**************************************************************************
 377 MII utilities - dump mii registers
 378 ***************************************************************************/
 379 static void
 380 gt6426x_dump_mii(bd_t *bis, unsigned short phy)
 381 {
 382         printf("mii reg 0 - 3:   %04x %04x %04x %04x\n",
 383                 miiphy_read_ret(phy, 0x0),
 384                 miiphy_read_ret(phy, 0x1),
 385                 miiphy_read_ret(phy, 0x2),
 386                 miiphy_read_ret(phy, 0x3)
 387                 );
 388         printf("        4 - 7:   %04x %04x %04x %04x\n",
 389                 miiphy_read_ret(phy, 0x4),
 390                 miiphy_read_ret(phy, 0x5),
 391                 miiphy_read_ret(phy, 0x6),
 392                 miiphy_read_ret(phy, 0x7)
 393                 );
 394         printf("        8:       %04x\n",
 395                 miiphy_read_ret(phy, 0x8)
 396                 );
 397         printf("        16-19:   %04x %04x %04x %04x\n",
 398                 miiphy_read_ret(phy, 0x10),
 399                 miiphy_read_ret(phy, 0x11),
 400                 miiphy_read_ret(phy, 0x12),
 401                 miiphy_read_ret(phy, 0x13)
 402                 );
 403         printf("        20,30:   %04x %04x\n",
 404                 miiphy_read_ret(phy, 20),
 405                 miiphy_read_ret(phy, 30)
 406                 );
 407 }
 408 #endif
 409
 410 #ifdef RESTART_AUTONEG
 411
 412 /* If link is up && autoneg compleate, and if
 413  * GT and PHY disagree about link capabilitys,
 414  * restart autoneg - something screwy with FD/HD
 415  * unless we do this. */
 416 static void
 417 check_phy_state(struct eth_dev_s *p)
 418 {
 419         int bmsr = miiphy_read_ret(ether_port_phy_addr[p->dev], PHY_BMSR);
 420         int psr = GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + p->reg_base);
 421
 422         if ((psr & 1<<3) && (bmsr & PHY_BMSR_LS)) {
 423                 int nego = miiphy_read_ret(ether_port_phy_addr[p->dev], PHY_ANAR) &
 424                                 miiphy_read_ret(ether_port_phy_addr[p->dev], PHY_ANLPAR);
 425                 int want;
 426
 427                 if (nego & PHY_ANLPAR_TXFD) {
 428                         want = 0x3;
 429                         printf("MII: 100Base-TX, Full Duplex\n");
 430                 } else if (nego & PHY_ANLPAR_TX) {
 431                         want = 0x1;
 432                         printf("MII: 100Base-TX, Half Duplex\n");
 433                 } else if (nego & PHY_ANLPAR_10FD) {
 434                         want = 0x2;
 435                         printf("MII: 10Base-T, Full Duplex\n");
 436                 } else if (nego & PHY_ANLPAR_10) {
 437                         want = 0x0;
 438                         printf("MII: 10Base-T, Half Duplex\n");
 439                 } else {
 440                         printf("MII: Unknown link-foo! %x\n", nego);
 441                         return;
 442                 }
 443
 444                 if ((psr & 0x3) != want) {
 445                         printf("MII: GT thinks %x, PHY thinks %x, restarting autoneg..\n",
 446                                         psr & 0x3, want);
 447                         miiphy_write(ether_port_phy_addr[p->dev],0,
 448                                         miiphy_read_ret(ether_port_phy_addr[p->dev],0) | (1<<9));
 449                         udelay(10000);  /* the EVB's GT takes a while to notice phy
 450                                            went down and up */
 451                 }
 452         }
 453 }
 454 #endif
 455
 456 /**************************************************************************
 457 PROBE - Look for an adapter, this routine's visible to the outside
 458 ***************************************************************************/
 459 int
 460 gt6426x_eth_probe(void *v, bd_t *bis)
 461 {
 462         struct eth_device *wp = (struct eth_device *)v;
 463         struct eth_dev_s *p = (struct eth_dev_s *)wp->priv;
 464         int dev = p->dev;
 465         unsigned int reg_base = p->reg_base;
 466         unsigned long temp;
 467         int i;
 468
 469         if (( dev < 0 ) || ( dev >= GAL_ETH_DEVS ))
 470         {       /* This should never happen */
 471                 printf("%s: Invalid device %d\n", __FUNCTION__, dev );
 472                 return 0;
 473         }
 474
 475 #ifdef DEBUG
 476         printf ("%s: initializing %s\n", __FUNCTION__, wp->name );
 477         printf ("\nCOMM_CONTROL = %08x , COMM_CONF = %08x\n",
 478                 GTREGREAD(COMM_UNIT_ARBITER_CONTROL),
 479                 GTREGREAD(COMM_UNIT_ARBITER_CONFIGURATION_REGISTER));
 480 #endif
 481
 482         /* clear MIB counters */
 483         for(i=0;i<255; i++)
 484             temp=GTREGREAD(ETHERNET0_MIB_COUNTER_BASE + reg_base +i);
 485
 486 #ifdef CONFIG_INTEL_LXT97X
 487         /* for intel LXT972 */
 488
 489         /* led 1: 0x1=txact
 490            led 2: 0xc=link/rxact
 491            led 3: 0x2=rxact (N/C)
 492            strch: 0,2=30 ms, enable */
 493         miiphy_write(ether_port_phy_addr[p->dev], 20, 0x1c22);
 494
 495         /* 2.7ns port rise time */
 496         /*miiphy_write(ether_port_phy_addr[p->dev], 30, 0x0<<10); */
 497 #else
 498         /* already set up in mpsc.c */
 499         /*GT_REG_WRITE(MAIN_ROUTING_REGISTER, 0x7ffe38);        /  b400 */
 500
 501         /* already set up in sdram_init.S... */
 502         /* MPSC0, MPSC1, RMII */
 503         /*GT_REG_WRITE(SERIAL_PORT_MULTIPLEX, 0x1102);          /  f010 */
 504 #endif
 505         GT_REG_WRITE(ETHERNET_PHY_ADDRESS_REGISTER,
 506              ether_port_phy_addr[0]     |
 507             (ether_port_phy_addr[1]<<5) |
 508             (ether_port_phy_addr[2]<<10));                      /* 2000 */
 509
 510         /* 13:12 -   10: 4x64bit burst  (cache line size = 32 bytes)
 511          *    9  -    1: RIFB - interrupt on frame boundaries only
 512          *  6:7  -   00: big endian rx and tx
 513          *  5:2  - 1111: 15 retries */
 514         GT_REG_WRITE(ETHERNET0_SDMA_CONFIGURATION_REGISTER + reg_base,
 515                 (2<<12) | (1<<9) | (0xf<<2) );                  /* 2440 */
 516
 517 #ifndef USE_SOFTWARE_CACHE_MANAGEMENT
 518         /* enable rx/tx desc/buffer cache snoop */
 519         GT_REG_READ(ETHERNET_0_ADDRESS_CONTROL_LOW + dev*0x20,
 520                 &temp);                                         /* f200 */
 521         temp|= (1<<6)| (1<<14)| (1<<22)| (1<<30);
 522         GT_REG_WRITE(ETHERNET_0_ADDRESS_CONTROL_LOW + dev*0x20,
 523                 temp);
 524 #endif
 525
 526         /* 31  28 27  24 23  20 19  16
 527          *  0000   0000   0000   0000   [0004]
 528          * 15  12 11  8   7  4   3  0
 529          *  1000   1101   0000   0000   [4d00]
 530          *    20 - 0=MII 1=RMII
 531          *    19 - 0=speed autoneg
 532          * 15:14 - framesize 1536 (GT6426x_ETH_BUF_SIZE)
 533          *    11 - no force link pass
 534          *    10 - 1=disable fctl autoneg
 535          *     8 - override prio ?? */
 536         temp = 0x00004d00;
 537 #ifndef CONFIG_ETHER_PORT_MII
 538         temp |= (1<<20);        /* RMII */
 539 #endif
 540         /* set En */
 541         GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER + reg_base,
 542                      temp);                             /* 2408 */
 543
 544         /* hardcode E1 also? */
 545         /* -- according to dox, this is safer due to extra pulldowns? */
 546         if (dev<2) {
 547         GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER + (dev+1) * 0x400,
 548                      temp);                             /* 2408 */
 549         }
 550
 551         /* wake up MAC */                                /* 2400 */
 552         GT_REG_READ(ETHERNET0_PORT_CONFIGURATION_REGISTER + reg_base, &temp);
 553         temp |= (1<<7);         /* enable port */
 554 #ifdef CONFIG_GT_USE_MAC_HASH_TABLE
 555         temp |= (1<<12);        /* hash size 1/2k */
 556 #else
 557         temp |= 1;              /* promisc */
 558 #endif
 559         GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_REGISTER + reg_base, temp);
 560                                                         /* 2400 */
 561
 562 #ifdef RESTART_AUTONEG
 563         check_phy_state(p);
 564 #endif
 565
 566         printf("%s: Waiting for link up..\n", wp->name);
 567         temp = 10 * 1000;
 568         /* wait for link back up */
 569         while(!(GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + reg_base) & 8)
 570                         && (--temp > 0)){
 571             udelay(1000);       /* wait 1 ms */
 572         }
 573         if ( temp == 0) {
 574                 printf("%s: Failed!\n", wp->name);
 575                 return (0);
 576         }
 577
 578         printf("%s: OK!\n", wp->name);
 579
 580         p->tdn = 0;
 581         p->rdn = 0;
 582         p->eth_tx_desc[p->tdn].command_status = 0;
 583
 584         /* Initialize Rx Side */
 585         for (temp = 0; temp < NR; temp++) {
 586                 p->eth_rx_desc[temp].buff_pointer = p->eth_rx_buffer[temp];
 587                 p->eth_rx_desc[temp].buff_size_byte_count = GT6426x_ETH_BUF_SIZE<<16;
 588
 589                 /* GT96100 Owner */
 590                 p->eth_rx_desc[temp].command_status = 0x80000000;
 591                 p->eth_rx_desc[temp].next_desc =
 592                         (struct eth0_rx_desc_struct *)
 593                         &p->eth_rx_desc[(temp+1)%NR].buff_size_byte_count;
 594         }
 595
 596         FLUSH_DCACHE((unsigned int)&p->eth_tx_desc[0],
 597                      (unsigned int)&p->eth_tx_desc[NR]);
 598         FLUSH_DCACHE((unsigned int)&p->eth_rx_desc[0],
 599                      (unsigned int)&p->eth_rx_desc[NR]);
 600
 601         GT_REG_WRITE(ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 + reg_base,
 602                       (unsigned int) p->eth_tx_desc);
 603         GT_REG_WRITE(ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 + reg_base,
 604                       (unsigned int) p->eth_rx_desc);
 605         GT_REG_WRITE(ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 + reg_base,
 606                       (unsigned int) p->eth_rx_desc);
 607
 608 #ifdef DEBUG
 609         printf ("\nRx descriptor pointer is %08x %08x\n",
 610                 GTREGREAD(ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 + reg_base),
 611                 GTREGREAD(ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 + reg_base));
 612         printf ("\n\n%08x %08x\n",
 613                 (unsigned int)p->eth_rx_desc,p->eth_rx_desc[0].command_status);
 614
 615         printf ("Descriptor dump:\n");
 616         printf ("cmd status: %08x\n",p->eth_rx_desc[0].command_status);
 617         printf ("byte_count: %08x\n",p->eth_rx_desc[0].buff_size_byte_count);
 618         printf ("buff_ptr: %08x\n",(unsigned int)p->eth_rx_desc[0].buff_pointer);
 619         printf ("next_desc: %08x\n\n",(unsigned int)p->eth_rx_desc[0].next_desc);
 620         printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x0));
 621         printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x4));
 622         printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x8));
 623         printf ("%08x\n\n",
 624                 *(unsigned int *) ((unsigned int)p->eth_rx_desc + 0xc));
 625 #endif
 626
 627 #ifdef DEBUG
 628         gt6426x_dump_mii(bis,ether_port_phy_addr[p->dev]);
 629 #endif
 630
 631 #ifdef CONFIG_GT_USE_MAC_HASH_TABLE
 632         {
 633                 unsigned int hashtable_base;
 634             u8 *b = (u8 *)(wp->enetaddr);
 635                 u32 macH, macL;
 636
 637                 /* twist the MAC up into the way the discovery wants it */
 638                 macH= (b[0]<<8) | b[1];
 639             macL= (b[2]<<24) | (b[3]<<16) | (b[4]<<8) | b[5];
 640
 641             /* mode 0, size 0x800 */
 642             hashtable_base =initAddressTable(dev,0,1);
 643
 644             if(!hashtable_base) {
 645                         printf("initAddressTable failed\n");
 646                         return 0;
 647             }
 648
 649             addAddressTableEntry(dev, macH, macL, 1, 0);
 650             GT_REG_WRITE(ETHERNET0_HASH_TABLE_POINTER_REGISTER + reg_base,
 651                     hashtable_base);
 652         }
 653 #endif
 654
 655         /* Start Rx*/
 656         GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + reg_base, 0x00000080);
 657         printf("%s: gt6426x eth device %d init success \n", wp->name, dev );
 658         return 1;
 659 }
 660
 661 /* enter all the galileo ethernet devs into MULTI-BOOT */
 662 void
 663 gt6426x_eth_initialize(bd_t *bis)
 664 {
 665         struct eth_device *dev;
 666         struct eth_dev_s *p;
 667         int devnum, x, temp;
 668         char *s, *e, buf[64];
 669
 670 #ifdef DEBUG
 671         printf( "\n%s\n", __FUNCTION );
 672 #endif
 673
 674         for (devnum = 0; devnum < GAL_ETH_DEVS; devnum++) {
 675                 dev = calloc(sizeof(*dev), 1);
 676                 if (!dev) {
 677                         printf( "%s: gal_enet%d allocation failure, %s\n",
 678                                         __FUNCTION__, devnum, "eth_device structure");
 679                         return;
 680                 }
 681
 682                 /* must be less than NAMESIZE (16) */
 683                 sprintf(dev->name, "gal_enet%d", devnum);
 684
 685 #ifdef DEBUG
 686                 printf( "Initializing %s\n", dev->name );
 687 #endif
 688
 689                 /* Extract the MAC address from the environment */
 690                 switch (devnum)
 691                 {
 692                         case 0: s = "ethaddr"; break;
 693 #if (GAL_ETH_DEVS > 1)
 694                         case 1: s = "eth1addr"; break;
 695 #endif
 696 #if (GAL_ETH_DEVS > 2)
 697                         case 2: s = "eth2addr"; break;
 698 #endif
 699                         default: /* this should never happen */
 700                                 printf( "%s: Invalid device number %d\n",
 701                                                 __FUNCTION__, devnum );
 702                                 return;
 703                 }
 704
 705                 temp = getenv_r (s, buf, sizeof(buf));
 706                 s = (temp > 0) ? buf : NULL;
 707
 708 #ifdef DEBUG
 709                 printf ("Setting MAC %d to %s\n", devnum, s );
 710 #endif
 711                 for (x = 0; x < 6; ++x) {
 712                         dev->enetaddr[x] = s ? simple_strtoul(s, &e, 16) : 0;
 713                         if (s)
 714                                 s = (*e) ? e+1 : e;
 715                 }
 716
 717                 dev->init = (void*)gt6426x_eth_probe;
 718                 dev->halt = (void*)gt6426x_eth_reset;
 719                 dev->send = (void*)gt6426x_eth_transmit;
 720                 dev->recv = (void*)gt6426x_eth_poll;
 721
 722                 dev->priv = (void*)p = calloc( sizeof(*p), 1 );
 723                 if (!p)
 724                 {
 725                         printf( "%s: %s allocation failure, %s\n",
 726                                         __FUNCTION__, dev->name, "Private Device Structure");
 727                         free(dev);
 728                         return;
 729                 }
 730
 731                 p->dev = devnum;
 732                 p->tdn=0;
 733                 p->rdn=0;
 734                 p->reg_base = devnum * ETHERNET_PORTS_DIFFERENCE_OFFSETS;
 735
 736                 p->eth_tx_desc =
 737                         (eth0_tx_desc_single *)
 738                         (((unsigned int) malloc(sizeof (eth0_tx_desc_single) *
 739                                                 (NT+1)) & 0xfffffff0) + 0x10);
 740                 if (!p)
 741                 {
 742                         printf( "%s: %s allocation failure, %s\n",
 743                                         __FUNCTION__, dev->name, "Tx Descriptor");
 744                         free(dev);
 745                         return;
 746                 }
 747
 748                 p->eth_rx_desc =
 749                         (eth0_rx_desc_single *)
 750                         (((unsigned int) malloc(sizeof (eth0_rx_desc_single) *
 751                                                 (NR+1)) & 0xfffffff0) + 0x10);
 752                 if (!p->eth_rx_desc)
 753                 {
 754                         printf( "%s: %s allocation failure, %s\n",
 755                                         __FUNCTION__, dev->name, "Rx Descriptor");
 756                         free(dev);
 757                         free(p);
 758                         return;
 759                 }
 760
 761                 p->eth_tx_buffer =
 762                         (char *) (((unsigned int) malloc(GT6426x_ETH_BUF_SIZE) & 0xfffffff0) + 0x10);
 763                 if (!p->eth_tx_buffer)
 764                 {
 765                         printf( "%s: %s allocation failure, %s\n",
 766                                         __FUNCTION__, dev->name, "Tx Bufffer");
 767                         free(dev);
 768                         free(p);
 769                         free(p->eth_rx_desc);
 770                         return;
 771                 }
 772
 773                 for (temp = 0 ; temp < NR ; temp ++) {
 774                         p->eth_rx_buffer[temp] =
 775                                 (char *)
 776                                 (((unsigned int) malloc(GT6426x_ETH_BUF_SIZE) & 0xfffffff0) + 0x10);
 777                         if (!p->eth_rx_buffer[temp])
 778                         {
 779                                 printf( "%s: %s allocation failure, %s\n",
 780                                                 __FUNCTION__, dev->name, "Rx Buffers");
 781                                 free(dev);
 782                                 free(p);
 783                                 free(p->eth_tx_buffer);
 784                                 free(p->eth_rx_desc);
 785                                 free(p->eth_tx_desc);
 786                                 while (temp >= 0)
 787                                         free(p->eth_rx_buffer[--temp]);
 788                                 return;
 789                         }
 790                 }
 791
 792
 793                 eth_register(dev);
 794         }
 795 }
 796 #endif /* CFG_CMD_NET && CONFIG_NET_MULTI */