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[profile/mobile/platform/kernel/u-boot-tm1.git] / board / evb64260 / eth.c
1 /**************************************************************************
2 Etherboot -  BOOTP/TFTP Bootstrap Program
3 Skeleton NIC driver for Etherboot
4 ***************************************************************************/
5
6 /*
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2, or (at
10  * your option) any later version.
11  */
12
13 /*
14  * This file is a modified version from the Galileo polled mode
15  * network driver for the ethernet contained within the GT64260
16  * chip. It has been modified to fit into the U-Boot framework, from
17  * the original (etherboot) setup.  Also, additional cleanup and features
18  * were added.
19  *
20  * - Josh Huber <huber@mclx.com>
21  */
22
23 #include <common.h>
24 #include <malloc.h>
25 #include <galileo/gt64260R.h>
26 #include <galileo/core.h>
27 #include <asm/cache.h>
28 #include <miiphy.h>
29 #include <net.h>
30 #include <netdev.h>
31
32 #include "eth.h"
33 #include "eth_addrtbl.h"
34
35 #if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
36
37 #define GT6426x_ETH_BUF_SIZE    1536
38
39 /* if you like verbose output, turn this on! */
40 #undef DEBUG
41
42 /* Restart autoneg if we detect link is up on phy init. */
43
44 /*
45  * The GT doc's say that after Rst is deasserted, and the PHY
46  * reports autoneg complete, it runs through its autoneg
47  * procedures. This doesn't seem to be the case for MII
48  * PHY's. To work around this check for link up && autoneg
49  * complete when initilizing the port. If they are both set,
50  * then restart PHY autoneg. Of course, it may be something
51  * completly different.
52  */
53 #ifdef CONFIG_ETHER_PORT_MII
54 # define RESTART_AUTONEG
55 #endif
56
57 /* do this if you dont want to use snooping */
58 #define USE_SOFTWARE_CACHE_MANAGEMENT
59
60 #ifdef USE_SOFTWARE_CACHE_MANAGEMENT
61 #define FLUSH_DCACHE(a,b)                if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
62 #define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));}
63 #define INVALIDATE_DCACHE(a,b)           if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));}
64 #else
65 /* bummer - w/o flush, nothing works, even with snooping - FIXME */
66 /* #define FLUSH_DCACHE(a,b) */
67 #define FLUSH_DCACHE(a,b)                if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
68 #define FLUSH_AND_INVALIDATE_DCACHE(a,b)
69 #define INVALIDATE_DCACHE(a,b)
70 #endif
71 struct eth_dev_s {
72         eth0_tx_desc_single *eth_tx_desc;
73         eth0_rx_desc_single *eth_rx_desc;
74         char *eth_tx_buffer;
75         char *eth_rx_buffer[NR];
76         int tdn, rdn;
77         int dev;
78         unsigned int reg_base;
79 };
80
81
82 #ifdef CONFIG_INTEL_LXT97X
83 /* for intel LXT972 */
84 static const char ether_port_phy_addr[3]={0,1,2};
85 #else
86 static const char ether_port_phy_addr[3]={4,5,6};
87 #endif
88
89 /* MII PHY access routines are common for all i/f, use gal_ent0 */
90 #define GT6426x_MII_DEVNAME     "gal_enet0"
91
92 int gt6426x_miiphy_read(const char *devname, unsigned char phy,
93                 unsigned char reg, unsigned short *val);
94
95 static inline unsigned short
96 miiphy_read_ret(unsigned short phy, unsigned short reg)
97 {
98     unsigned short val;
99     gt6426x_miiphy_read(GT6426x_MII_DEVNAME,phy,reg,&val);
100     return val;
101 }
102
103
104 /**************************************************************************
105 RESET - Reset adapter
106 ***************************************************************************/
107 void
108 gt6426x_eth_reset(void *v)
109 {
110         /*  we should do something here...
111         struct eth_device *wp = (struct eth_device *)v;
112         struct eth_dev_s *p = wp->priv;
113         */
114
115         printf ("RESET\n");
116         /* put the card in its initial state */
117 }
118
119 static void gt6426x_handle_SMI(struct eth_dev_s *p, unsigned int icr)
120 {
121 #ifdef DEBUG
122     printf("SMI interrupt: ");
123
124     if(icr&0x20000000) {
125         printf("SMI done\n");
126     }
127 #endif
128
129     if(icr&0x10000000) {
130         unsigned int psr;
131         psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + p->reg_base);
132 #ifdef DEBUG
133         printf("PHY state change:\n"
134                "  GT:%s:%s:%s:%s\n",
135                 psr&1?"100":" 10",
136                 psr&8?" Link":"nLink",
137                 psr&2?"FD":"HD",
138                 psr&4?" FC":"nFC");
139
140 #ifdef CONFIG_INTEL_LXT97X /* non-standard mii reg (intel lxt972a) */
141         {
142         unsigned short mii_11;
143         mii_11=miiphy_read_ret(ether_port_phy_addr[p->dev],0x11);
144
145         printf(" mii:%s:%s:%s:%s %s:%s %s\n",
146                 mii_11&(1<<14)?"100":" 10",
147                 mii_11&(1<<10)?" Link":"nLink",
148                 mii_11&(1<<9)?"FD":"HD",
149                 mii_11&(1<<4)?" FC":"nFC",
150
151                 mii_11&(1<<7)?"ANc":"ANnc",
152                 mii_11&(1<<8)?"AN":"Manual",
153                 ""
154                 );
155         }
156 #endif /* CONFIG_INTEL_LXT97X */
157 #endif /* DEBUG */
158     }
159 }
160
161 static int
162 gt6426x_eth_receive(struct eth_dev_s *p,unsigned int icr)
163 {
164         int eth_len=0;
165         char *eth_data;
166
167         eth0_rx_desc_single *rx = &p->eth_rx_desc[(p->rdn)];
168
169         INVALIDATE_DCACHE((unsigned int)rx,(unsigned int)(rx+1));
170
171         if (rx->command_status & 0x80000000) {
172                 return 0; /* No packet received */
173         }
174
175         eth_len = (unsigned int)
176                 (rx->buff_size_byte_count) & 0x0000ffff;
177         eth_data = (char *) p->eth_rx_buffer[p->rdn];
178
179 #ifdef DEBUG
180         if (eth_len) {
181                 printf ("%s: Recived %d byte Packet @ 0x%p\n",
182                         __FUNCTION__, eth_len, eth_data);
183         }
184 #endif
185         /*
186          * packet is now in:
187          * eth0_rx_buffer[RDN_ETH0];
188          */
189
190         /* let the upper layer handle the packet */
191         NetReceive ((uchar *)eth_data, eth_len);
192
193         rx->buff_size_byte_count = GT6426x_ETH_BUF_SIZE<<16;
194
195
196         /* GT96100 Owner */
197         rx->command_status = 0x80000000;
198
199         FLUSH_DCACHE((unsigned int)rx,(unsigned int)(rx+1));
200
201         p->rdn ++;
202         if (p->rdn == NR) {p->rdn = 0;}
203
204         sync();
205
206         /* Start Rx*/
207         GT_REG_WRITE (ETHERNET0_SDMA_COMMAND_REGISTER + p->reg_base, 0x00000080);
208
209 #ifdef DEBUG
210         {
211             int i;
212             for (i=0;i<12;i++) {
213                 printf(" %02x", eth_data[i]);
214             }
215         }
216         printf(": %d bytes\n", eth_len);
217 #endif
218         INVALIDATE_DCACHE((unsigned int)eth_data,
219                 (unsigned int)eth_data+eth_len);
220         return eth_len;
221 }
222
223 /**************************************************************************
224 POLL - look for an rx frame, handle other conditions
225 ***************************************************************************/
226 int
227 gt6426x_eth_poll(void *v)
228 {
229         struct eth_device *wp = (struct eth_device *)v;
230         struct eth_dev_s *p = wp->priv;
231         unsigned int icr=GTREGREAD(ETHERNET0_INTERRUPT_CAUSE_REGISTER + p->reg_base);
232
233         if(icr) {
234             GT_REG_WRITE(ETHERNET0_INTERRUPT_CAUSE_REGISTER +p->reg_base, 0);
235 #ifdef DEBUG
236             printf("poll got ICR %08x\n", icr);
237 #endif
238             /* SMI done or PHY state change*/
239             if(icr&0x30000000) gt6426x_handle_SMI(p, icr);
240         }
241         /* always process. We aren't using RX interrupts */
242         return gt6426x_eth_receive(p, icr);
243 }
244
245 /**************************************************************************
246 TRANSMIT - Transmit a frame
247 ***************************************************************************/
248 int
249 gt6426x_eth_transmit(void *v, volatile char *p, unsigned int s)
250 {
251         struct eth_device *wp = (struct eth_device *)v;
252         struct eth_dev_s *dev = (struct eth_dev_s *)wp->priv;
253 #ifdef DEBUG
254         unsigned int old_command_stat,old_psr;
255 #endif
256         eth0_tx_desc_single *tx = &dev->eth_tx_desc[dev->tdn];
257
258         /* wait for tx to be ready */
259         INVALIDATE_DCACHE((unsigned int)tx,(unsigned int)(tx+1));
260         while (tx->command_status & 0x80000000) {
261             int i;
262             for(i=0;i<1000;i++);
263                         INVALIDATE_DCACHE((unsigned int)tx,(unsigned int)(tx+1));
264         }
265
266         GT_REG_WRITE (ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 + dev->reg_base,
267                       (unsigned int)tx);
268
269 #ifdef DEBUG
270         printf("copying to tx_buffer [%p], length %x, desc = %p\n",
271                dev->eth_tx_buffer, s, dev->eth_tx_desc);
272 #endif
273         memcpy(dev->eth_tx_buffer, (char *) p, s);
274
275         tx->buff_pointer = (uchar *)dev->eth_tx_buffer;
276         tx->bytecount_reserved = ((__u16)s) << 16;
277
278         /*    31 - own
279          *    22 - gencrc
280          * 18:16 - pad, last, first */
281         tx->command_status = (1<<31) | (1<<22) | (7<<16);
282 #if 0
283         /* FEr #18 */
284         tx->next_desc = NULL;
285 #else
286         tx->next_desc =
287                 (struct eth0_tx_desc_struct *)
288                 &dev->eth_tx_desc[(dev->tdn+1)%NT].bytecount_reserved;
289
290         /* cpu owned */
291         dev->eth_tx_desc[(dev->tdn+1)%NT].command_status = (7<<16);     /* pad, last, first */
292 #endif
293
294 #ifdef DEBUG
295         old_command_stat=tx->command_status,
296         old_psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + dev->reg_base);
297 #endif
298
299         FLUSH_DCACHE((unsigned int)tx,
300                 (unsigned int)&dev->eth_tx_desc[(dev->tdn+2)%NT]);
301
302         FLUSH_DCACHE((unsigned int)dev->eth_tx_buffer,(unsigned int)dev->eth_tx_buffer+s);
303
304         GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + dev->reg_base, 0x01000000);
305
306 #ifdef DEBUG
307         {
308             unsigned int command_stat=0;
309             printf("cmd_stat: %08x PSR: %08x\n", old_command_stat, old_psr);
310             /* wait for tx to be ready */
311             do {
312                 unsigned int psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + dev->reg_base);
313                 command_stat=tx->command_status;
314                 if(command_stat!=old_command_stat || psr !=old_psr) {
315                     printf("cmd_stat: %08x PSR: %08x\n", command_stat, psr);
316                     old_command_stat = command_stat;
317                     old_psr = psr;
318                 }
319                 /* gt6426x_eth0_poll(); */
320             } while (command_stat & 0x80000000);
321
322             printf("sent %d byte frame\n", s);
323
324             if((command_stat & (3<<15)) == 3) {
325                 printf("frame had error (stat=%08x)\n", command_stat);
326             }
327         }
328 #endif
329         return 0;
330 }
331
332 /**************************************************************************
333 DISABLE - Turn off ethernet interface
334 ***************************************************************************/
335 void
336 gt6426x_eth_disable(void *v)
337 {
338         struct eth_device *wp = (struct eth_device *)v;
339         struct eth_dev_s *p = (struct eth_dev_s *)wp->priv;
340
341         GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + p->reg_base, 0x80008000);
342 }
343
344 /**************************************************************************
345 MII utilities - write: write to an MII register via SMI
346 ***************************************************************************/
347 int
348 gt6426x_miiphy_write(const char *devname, unsigned char phy,
349                 unsigned char reg, unsigned short data)
350 {
351     unsigned int temp= (reg<<21) | (phy<<16) | data;
352
353     while(GTREGREAD(ETHERNET_SMI_REGISTER) & (1<<28));  /* wait for !Busy */
354
355     GT_REG_WRITE(ETHERNET_SMI_REGISTER, temp);
356     return 0;
357 }
358
359 /**************************************************************************
360 MII utilities - read: read from an MII register via SMI
361 ***************************************************************************/
362 int
363 gt6426x_miiphy_read(const char *devname, unsigned char phy,
364                 unsigned char reg, unsigned short *val)
365 {
366     unsigned int temp= (reg<<21) | (phy<<16) | 1<<26;
367
368     while(GTREGREAD(ETHERNET_SMI_REGISTER) & (1<<28));  /* wait for !Busy */
369
370     GT_REG_WRITE(ETHERNET_SMI_REGISTER, temp);
371
372     while(1) {
373         temp=GTREGREAD(ETHERNET_SMI_REGISTER);
374         if(temp & (1<<27)) break;               /* wait for ReadValid */
375     }
376     *val = temp & 0xffff;
377
378     return 0;
379 }
380
381 #ifdef DEBUG
382 /**************************************************************************
383 MII utilities - dump mii registers
384 ***************************************************************************/
385 static void
386 gt6426x_dump_mii(bd_t *bis, unsigned short phy)
387 {
388         printf("mii reg 0 - 3:   %04x %04x %04x %04x\n",
389                 miiphy_read_ret(phy, 0x0),
390                 miiphy_read_ret(phy, 0x1),
391                 miiphy_read_ret(phy, 0x2),
392                 miiphy_read_ret(phy, 0x3)
393                 );
394         printf("        4 - 7:   %04x %04x %04x %04x\n",
395                 miiphy_read_ret(phy, 0x4),
396                 miiphy_read_ret(phy, 0x5),
397                 miiphy_read_ret(phy, 0x6),
398                 miiphy_read_ret(phy, 0x7)
399                 );
400         printf("        8:       %04x\n",
401                 miiphy_read_ret(phy, 0x8)
402                 );
403         printf("        16-19:   %04x %04x %04x %04x\n",
404                 miiphy_read_ret(phy, 0x10),
405                 miiphy_read_ret(phy, 0x11),
406                 miiphy_read_ret(phy, 0x12),
407                 miiphy_read_ret(phy, 0x13)
408                 );
409         printf("        20,30:   %04x %04x\n",
410                 miiphy_read_ret(phy, 20),
411                 miiphy_read_ret(phy, 30)
412                 );
413 }
414 #endif
415
416 #ifdef RESTART_AUTONEG
417
418 /* If link is up && autoneg compleate, and if
419  * GT and PHY disagree about link capabilitys,
420  * restart autoneg - something screwy with FD/HD
421  * unless we do this. */
422 static void
423 check_phy_state(struct eth_dev_s *p)
424 {
425         int bmsr = miiphy_read_ret(ether_port_phy_addr[p->dev], PHY_BMSR);
426         int psr = GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + p->reg_base);
427
428         if ((psr & 1<<3) && (bmsr & PHY_BMSR_LS)) {
429                 int nego = miiphy_read_ret(ether_port_phy_addr[p->dev], PHY_ANAR) &
430                                 miiphy_read_ret(ether_port_phy_addr[p->dev], PHY_ANLPAR);
431                 int want;
432
433                 if (nego & PHY_ANLPAR_TXFD) {
434                         want = 0x3;
435                         printf("MII: 100Base-TX, Full Duplex\n");
436                 } else if (nego & PHY_ANLPAR_TX) {
437                         want = 0x1;
438                         printf("MII: 100Base-TX, Half Duplex\n");
439                 } else if (nego & PHY_ANLPAR_10FD) {
440                         want = 0x2;
441                         printf("MII: 10Base-T, Full Duplex\n");
442                 } else if (nego & PHY_ANLPAR_10) {
443                         want = 0x0;
444                         printf("MII: 10Base-T, Half Duplex\n");
445                 } else {
446                         printf("MII: Unknown link-foo! %x\n", nego);
447                         return;
448                 }
449
450                 if ((psr & 0x3) != want) {
451                         printf("MII: GT thinks %x, PHY thinks %x, restarting autoneg..\n",
452                                         psr & 0x3, want);
453                         miiphy_write(GT6426x_MII_DEVNAME,ether_port_phy_addr[p->dev],0,
454                                         miiphy_read_ret(ether_port_phy_addr[p->dev],0) | (1<<9));
455                         udelay(10000);  /* the EVB's GT takes a while to notice phy
456                                            went down and up */
457                 }
458         }
459 }
460 #endif
461
462 /**************************************************************************
463 PROBE - Look for an adapter, this routine's visible to the outside
464 ***************************************************************************/
465 int
466 gt6426x_eth_probe(void *v, bd_t *bis)
467 {
468         struct eth_device *wp = (struct eth_device *)v;
469         struct eth_dev_s *p = (struct eth_dev_s *)wp->priv;
470         int dev = p->dev;
471         unsigned int reg_base = p->reg_base;
472         unsigned long temp;
473         int i;
474
475         if (( dev < 0 ) || ( dev >= GAL_ETH_DEVS ))
476         {       /* This should never happen */
477                 printf("%s: Invalid device %d\n", __FUNCTION__, dev );
478                 return 0;
479         }
480
481 #ifdef DEBUG
482         printf ("%s: initializing %s\n", __FUNCTION__, wp->name );
483         printf ("\nCOMM_CONTROL = %08x , COMM_CONF = %08x\n",
484                 GTREGREAD(COMM_UNIT_ARBITER_CONTROL),
485                 GTREGREAD(COMM_UNIT_ARBITER_CONFIGURATION_REGISTER));
486 #endif
487
488         /* clear MIB counters */
489         for(i=0;i<255; i++)
490             temp=GTREGREAD(ETHERNET0_MIB_COUNTER_BASE + reg_base +i);
491
492 #ifdef CONFIG_INTEL_LXT97X
493         /* for intel LXT972 */
494
495         /* led 1: 0x1=txact
496            led 2: 0xc=link/rxact
497            led 3: 0x2=rxact (N/C)
498            strch: 0,2=30 ms, enable */
499         miiphy_write(GT6426x_MII_DEVNAME,ether_port_phy_addr[p->dev], 20, 0x1c22);
500
501         /* 2.7ns port rise time */
502         /*miiphy_write(ether_port_phy_addr[p->dev], 30, 0x0<<10); */
503 #else
504         /* already set up in mpsc.c */
505         /*GT_REG_WRITE(MAIN_ROUTING_REGISTER, 0x7ffe38);        /  b400 */
506
507         /* already set up in sdram_init.S... */
508         /* MPSC0, MPSC1, RMII */
509         /*GT_REG_WRITE(SERIAL_PORT_MULTIPLEX, 0x1102);          /  f010 */
510 #endif
511         GT_REG_WRITE(ETHERNET_PHY_ADDRESS_REGISTER,
512              ether_port_phy_addr[0]     |
513             (ether_port_phy_addr[1]<<5) |
514             (ether_port_phy_addr[2]<<10));                      /* 2000 */
515
516         /* 13:12 -   10: 4x64bit burst  (cache line size = 32 bytes)
517          *    9  -    1: RIFB - interrupt on frame boundaries only
518          *  6:7  -   00: big endian rx and tx
519          *  5:2  - 1111: 15 retries */
520         GT_REG_WRITE(ETHERNET0_SDMA_CONFIGURATION_REGISTER + reg_base,
521                 (2<<12) | (1<<9) | (0xf<<2) );                  /* 2440 */
522
523 #ifndef USE_SOFTWARE_CACHE_MANAGEMENT
524         /* enable rx/tx desc/buffer cache snoop */
525         GT_REG_READ(ETHERNET_0_ADDRESS_CONTROL_LOW + dev*0x20,
526                 &temp);                                         /* f200 */
527         temp|= (1<<6)| (1<<14)| (1<<22)| (1<<30);
528         GT_REG_WRITE(ETHERNET_0_ADDRESS_CONTROL_LOW + dev*0x20,
529                 temp);
530 #endif
531
532         /* 31  28 27  24 23  20 19  16
533          *  0000   0000   0000   0000   [0004]
534          * 15  12 11  8   7  4   3  0
535          *  1000   1101   0000   0000   [4d00]
536          *    20 - 0=MII 1=RMII
537          *    19 - 0=speed autoneg
538          * 15:14 - framesize 1536 (GT6426x_ETH_BUF_SIZE)
539          *    11 - no force link pass
540          *    10 - 1=disable fctl autoneg
541          *     8 - override prio ?? */
542         temp = 0x00004d00;
543 #ifndef CONFIG_ETHER_PORT_MII
544         temp |= (1<<20);        /* RMII */
545 #endif
546         /* set En */
547         GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER + reg_base,
548                      temp);                             /* 2408 */
549
550         /* hardcode E1 also? */
551         /* -- according to dox, this is safer due to extra pulldowns? */
552         if (dev<2) {
553         GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER + (dev+1) * 0x400,
554                      temp);                             /* 2408 */
555         }
556
557         /* wake up MAC */                                /* 2400 */
558         GT_REG_READ(ETHERNET0_PORT_CONFIGURATION_REGISTER + reg_base, &temp);
559         temp |= (1<<7);         /* enable port */
560 #ifdef CONFIG_GT_USE_MAC_HASH_TABLE
561         temp |= (1<<12);        /* hash size 1/2k */
562 #else
563         temp |= 1;              /* promisc */
564 #endif
565         GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_REGISTER + reg_base, temp);
566                                                         /* 2400 */
567
568 #ifdef RESTART_AUTONEG
569         check_phy_state(p);
570 #endif
571
572         printf("%s: Waiting for link up..\n", wp->name);
573         temp = 10 * 1000;
574         /* wait for link back up */
575         while(!(GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + reg_base) & 8)
576                         && (--temp > 0)){
577             udelay(1000);       /* wait 1 ms */
578         }
579         if ( temp == 0) {
580                 printf("%s: Failed!\n", wp->name);
581                 return (0);
582         }
583
584         printf("%s: OK!\n", wp->name);
585
586         p->tdn = 0;
587         p->rdn = 0;
588         p->eth_tx_desc[p->tdn].command_status = 0;
589
590         /* Initialize Rx Side */
591         for (temp = 0; temp < NR; temp++) {
592                 p->eth_rx_desc[temp].buff_pointer = (uchar *)p->eth_rx_buffer[temp];
593                 p->eth_rx_desc[temp].buff_size_byte_count = GT6426x_ETH_BUF_SIZE<<16;
594
595                 /* GT96100 Owner */
596                 p->eth_rx_desc[temp].command_status = 0x80000000;
597                 p->eth_rx_desc[temp].next_desc =
598                         (struct eth0_rx_desc_struct *)
599                         &p->eth_rx_desc[(temp+1)%NR].buff_size_byte_count;
600         }
601
602         FLUSH_DCACHE((unsigned int)&p->eth_tx_desc[0],
603                      (unsigned int)&p->eth_tx_desc[NR]);
604         FLUSH_DCACHE((unsigned int)&p->eth_rx_desc[0],
605                      (unsigned int)&p->eth_rx_desc[NR]);
606
607         GT_REG_WRITE(ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 + reg_base,
608                       (unsigned int) p->eth_tx_desc);
609         GT_REG_WRITE(ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 + reg_base,
610                       (unsigned int) p->eth_rx_desc);
611         GT_REG_WRITE(ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 + reg_base,
612                       (unsigned int) p->eth_rx_desc);
613
614 #ifdef DEBUG
615         printf ("\nRx descriptor pointer is %08x %08x\n",
616                 GTREGREAD(ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 + reg_base),
617                 GTREGREAD(ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 + reg_base));
618         printf ("\n\n%08x %08x\n",
619                 (unsigned int)p->eth_rx_desc,p->eth_rx_desc[0].command_status);
620
621         printf ("Descriptor dump:\n");
622         printf ("cmd status: %08x\n",p->eth_rx_desc[0].command_status);
623         printf ("byte_count: %08x\n",p->eth_rx_desc[0].buff_size_byte_count);
624         printf ("buff_ptr: %08x\n",(unsigned int)p->eth_rx_desc[0].buff_pointer);
625         printf ("next_desc: %08x\n\n",(unsigned int)p->eth_rx_desc[0].next_desc);
626         printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x0));
627         printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x4));
628         printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x8));
629         printf ("%08x\n\n",
630                 *(unsigned int *) ((unsigned int)p->eth_rx_desc + 0xc));
631 #endif
632
633 #ifdef DEBUG
634         gt6426x_dump_mii(bis,ether_port_phy_addr[p->dev]);
635 #endif
636
637 #ifdef CONFIG_GT_USE_MAC_HASH_TABLE
638         {
639                 unsigned int hashtable_base;
640             u8 *b = (u8 *)(wp->enetaddr);
641                 u32 macH, macL;
642
643                 /* twist the MAC up into the way the discovery wants it */
644                 macH= (b[0]<<8) | b[1];
645             macL= (b[2]<<24) | (b[3]<<16) | (b[4]<<8) | b[5];
646
647             /* mode 0, size 0x800 */
648             hashtable_base =initAddressTable(dev,0,1);
649
650             if(!hashtable_base) {
651                         printf("initAddressTable failed\n");
652                         return 0;
653             }
654
655             addAddressTableEntry(dev, macH, macL, 1, 0);
656             GT_REG_WRITE(ETHERNET0_HASH_TABLE_POINTER_REGISTER + reg_base,
657                     hashtable_base);
658         }
659 #endif
660
661         /* Start Rx*/
662         GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + reg_base, 0x00000080);
663         printf("%s: gt6426x eth device %d init success \n", wp->name, dev );
664         return 1;
665 }
666
667 /* enter all the galileo ethernet devs into MULTI-BOOT */
668 void
669 gt6426x_eth_initialize(bd_t *bis)
670 {
671         struct eth_device *dev;
672         struct eth_dev_s *p;
673         int devnum, x, temp;
674         char *s, *e, buf[64];
675
676 #ifdef DEBUG
677         printf( "\n%s\n", __FUNCTION );
678 #endif
679
680         for (devnum = 0; devnum < GAL_ETH_DEVS; devnum++) {
681                 dev = calloc(sizeof(*dev), 1);
682                 if (!dev) {
683                         printf( "%s: gal_enet%d allocation failure, %s\n",
684                                         __FUNCTION__, devnum, "eth_device structure");
685                         return;
686                 }
687
688                 /* must be less than NAMESIZE (16) */
689                 sprintf(dev->name, "gal_enet%d", devnum);
690
691 #ifdef DEBUG
692                 printf( "Initializing %s\n", dev->name );
693 #endif
694
695                 /* Extract the MAC address from the environment */
696                 switch (devnum)
697                 {
698                         case 0: s = "ethaddr"; break;
699 #if (GAL_ETH_DEVS > 1)
700                         case 1: s = "eth1addr"; break;
701 #endif
702 #if (GAL_ETH_DEVS > 2)
703                         case 2: s = "eth2addr"; break;
704 #endif
705                         default: /* this should never happen */
706                                 printf( "%s: Invalid device number %d\n",
707                                                 __FUNCTION__, devnum );
708                                 return;
709                 }
710
711                 temp = getenv_f(s, buf, sizeof(buf));
712                 s = (temp > 0) ? buf : NULL;
713
714 #ifdef DEBUG
715                 printf ("Setting MAC %d to %s\n", devnum, s );
716 #endif
717                 for (x = 0; x < 6; ++x) {
718                         dev->enetaddr[x] = s ? simple_strtoul(s, &e, 16) : 0;
719                         if (s)
720                                 s = (*e) ? e+1 : e;
721                 }
722
723                 dev->init = (void*)gt6426x_eth_probe;
724                 dev->halt = (void*)gt6426x_eth_reset;
725                 dev->send = (void*)gt6426x_eth_transmit;
726                 dev->recv = (void*)gt6426x_eth_poll;
727
728                 p = calloc( sizeof(*p), 1 );
729                 dev->priv = (void*)p;
730                 if (!p)
731                 {
732                         printf( "%s: %s allocation failure, %s\n",
733                                         __FUNCTION__, dev->name, "Private Device Structure");
734                         free(dev);
735                         return;
736                 }
737
738                 p->dev = devnum;
739                 p->tdn=0;
740                 p->rdn=0;
741                 p->reg_base = devnum * ETHERNET_PORTS_DIFFERENCE_OFFSETS;
742
743                 p->eth_tx_desc =
744                         (eth0_tx_desc_single *)
745                         (((unsigned int) malloc(sizeof (eth0_tx_desc_single) *
746                                                 (NT+1)) & 0xfffffff0) + 0x10);
747                 if (!p)
748                 {
749                         printf( "%s: %s allocation failure, %s\n",
750                                         __FUNCTION__, dev->name, "Tx Descriptor");
751                         free(dev);
752                         return;
753                 }
754
755                 p->eth_rx_desc =
756                         (eth0_rx_desc_single *)
757                         (((unsigned int) malloc(sizeof (eth0_rx_desc_single) *
758                                                 (NR+1)) & 0xfffffff0) + 0x10);
759                 if (!p->eth_rx_desc)
760                 {
761                         printf( "%s: %s allocation failure, %s\n",
762                                         __FUNCTION__, dev->name, "Rx Descriptor");
763                         free(dev);
764                         free(p);
765                         return;
766                 }
767
768                 p->eth_tx_buffer =
769                         (char *) (((unsigned int) malloc(GT6426x_ETH_BUF_SIZE) & 0xfffffff0) + 0x10);
770                 if (!p->eth_tx_buffer)
771                 {
772                         printf( "%s: %s allocation failure, %s\n",
773                                         __FUNCTION__, dev->name, "Tx Bufffer");
774                         free(dev);
775                         free(p);
776                         free(p->eth_rx_desc);
777                         return;
778                 }
779
780                 for (temp = 0 ; temp < NR ; temp ++) {
781                         p->eth_rx_buffer[temp] =
782                                 (char *)
783                                 (((unsigned int) malloc(GT6426x_ETH_BUF_SIZE) & 0xfffffff0) + 0x10);
784                         if (!p->eth_rx_buffer[temp])
785                         {
786                                 printf( "%s: %s allocation failure, %s\n",
787                                                 __FUNCTION__, dev->name, "Rx Buffers");
788                                 free(dev);
789                                 free(p);
790                                 free(p->eth_tx_buffer);
791                                 free(p->eth_rx_desc);
792                                 free(p->eth_tx_desc);
793                                 while (temp >= 0)
794                                         free(p->eth_rx_buffer[--temp]);
795                                 return;
796                         }
797                 }
798
799
800                 eth_register(dev);
801 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
802                 miiphy_register(dev->name,
803                                 gt6426x_miiphy_read, gt6426x_miiphy_write);
804 #endif
805         }
806
807 }
808 #endif