1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2009 Renesas Solutions Corp.
4 * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
6 * board/espt/lowlevel_init.S
10 #include <asm/processor.h>
11 #include <asm/macro.h>
20 write32 WDTCSR_A, WDTCSR_D
22 write32 WDTST_A, WDTST_D
24 write32 WDTBST_A, WDTBST_D
26 write32 CCR_A, CCR_CACHE_ICI_D
28 write32 MMUCR_A, MMU_CONTROL_TI_D
30 write32 MSTPCR0_A, MSTPCR0_D
32 write32 MSTPCR1_A, MSTPCR1_D
34 write32 RAMCR_A, RAMCR_D
37 * Setting infomation from
38 * original ESPT-GIGA bootloader register
40 write32 MMSEL_A, MMSEL_D
49 write32 CS0BCR_A, CS0BCR_D
51 write32 CS0WCR_A, CS0WCR_D
57 /* set DDR-SDRAM dummy read */
58 write32 MMSEL_A, MMSEL_D
60 write32 MMSEL_A, CS0_A
62 /* set DDR-SDRAM bus/endian etc */
63 write32 MIM_U_A, MIM_U_D
65 write32 MIM_L_A, MIM_L_D0
67 write32 SDR_L_A, SDR_L_A_D0
69 write32 STR_L_A, STR_L_A_D0
71 /* DDR-SDRAM access control */
72 write32 MIM_L_A, MIM_L_D1
74 write32 SCR_L_A, SCR_L_A_D0
76 write32 SCR_L_A, SCR_L_A_D1
78 write32 EMRS_A, EMRS_D
80 write32 MRS1_A, MRS1_D
82 write32 MIM_U_A, MIM_U_D
84 write32 MIM_L_A, MIM_L_A_D2
86 write32 SCR_L_A, SCR_L_A_D2
88 write32 SCR_L_A, SCR_L_A_D2
90 write32 MRS2_A, MRS2_D
96 write16 PSEL0_A, PSEL0_D
98 write16 PSEL1_A, PSEL1_D
100 write16 PSEL2_A, PSEL2_D
102 write16 PSEL3_A, PSEL3_D
104 write16 PSEL4_A, PSEL4_D
106 write8 PADR_A, PADR_D
108 write16 PACR_A, PACR_D
110 write8 PBDR_A, PBDR_D
112 write16 PBCR_A, PBCR_D
114 write8 PCDR_A, PCDR_D
116 write16 PCCR_A, PCCR_D
118 write8 PDDR_A, PDDR_D
120 write16 PDCR_A, PDCR_D
122 write16 PECR_A, PECR_D
124 write16 PFCR_A, PFCR_D
126 write16 PGCR_A, PGCR_D
128 write16 PHCR_A, PHCR_D
130 write16 PICR_A, PICR_D
132 write8 PJDR_A, PJDR_D
134 write16 PJCR_A, PJCR_D
139 write8 PKDR_A, PKDR_D
141 write16 PKCR_A, PKCR_D
143 write16 PLCR_A, PLCR_D
145 write16 PMCR_A, PMCR_D
147 write16 PNCR_A, PNCR_D
149 write16 POCR_A, POCR_D
153 write32 ICR0_A, ICR0_D
155 write32 ICR1_A, ICR1_D
158 write32 USB_USBHSC_A, USB_USBHSC_D
160 write32 CCR_A, CCR_CACHE_D_2
167 /* GPIO Crontrol Register */
168 PACR_A: .long 0xFFEF0000
169 PBCR_A: .long 0xFFEF0002
170 PCCR_A: .long 0xFFEF0004
171 PDCR_A: .long 0xFFEF0006
172 PECR_A: .long 0xFFEF0008
173 PFCR_A: .long 0xFFEF000A
174 PGCR_A: .long 0xFFEF000C
175 PHCR_A: .long 0xFFEF000E
176 PICR_A: .long 0xFFEF0010
177 PJCR_A: .long 0xFFEF0012
178 PKCR_A: .long 0xFFEF0014
179 PLCR_A: .long 0xFFEF0016
180 PMCR_A: .long 0xFFEF0018
181 PNCR_A: .long 0xFFEF001A
182 POCR_A: .long 0xFFEF001C
184 /* GPIO Data Register */
185 PADR_A: .long 0xFFEF0020
186 PBDR_A: .long 0xFFEF0022
187 PCDR_A: .long 0xFFEF0024
188 PDDR_A: .long 0xFFEF0026
189 PJDR_A: .long 0xFFEF0032
190 PKDR_A: .long 0xFFEF0034
193 PADR_D: .long 0x00000000
196 PBDR_D: .long 0x00000000
199 PCDR_D: .long 0x00000000
202 PDDR_D: .long 0x00000000
209 PJDR_D: .long 0x00000006
212 PKDR_D: .long 0x00000000
221 PSEL0_A: .long 0xFFEF0070
222 PSEL1_A: .long 0xFFEF0072
223 PSEL2_A: .long 0xFFEF0074
224 PSEL3_A: .long 0xFFEF0076
225 PSEL4_A: .long 0xFFEF0078
226 PSEL0_D: .word 0x0001
227 PSEL1_D: .word 0x2400
228 PSEL2_D: .word 0x0000
229 PSEL3_D: .word 0x2421
230 PSEL4_D: .word 0x0000
233 MMSEL_A: .long 0xFE600020
234 BCR_A: .long 0xFF801000
235 CS0BCR_A: .long 0xFF802000
236 CS0WCR_A: .long 0xFF802008
237 ICR0_A: .long 0xFFD00000
238 ICR1_A: .long 0xFFD0001C
240 MMSEL_D: .long 0xA5A50000
241 BCR_D: .long 0x05000000
242 CS0BCR_D: .long 0x232306F0
243 CS0WCR_D: .long 0x00011104
244 ICR0_D: .long 0x80C00000
245 ICR1_D: .long 0x00020000
248 WDTST_A: .long 0xFFCC0000
249 WDTCSR_A: .long 0xFFCC0004
250 WDTBST_A: .long 0xFFCC0008
252 WDTST_D: .long 0x5A000FFF
253 WDTCSR_D: .long 0xA5000000
254 WDTBST_D: .long 0x55000000
257 CCR_A: .long 0xFF00001C
258 MMUCR_A: .long 0xFF000010
259 RAMCR_A: .long 0xFF000074
262 CCR_CACHE_ICI_D:.long 0x00000800
263 CCR_CACHE_D_2: .long 0x00000103
264 MMU_CONTROL_TI_D:.long 0x00000004
265 RAMCR_D: .long 0x00000200
267 /* Low power mode control Address */
268 MSTPCR0_A: .long 0xFFC80030
269 MSTPCR1_A: .long 0xFFC80038
270 /* Low power mode control Data */
271 MSTPCR0_D: .long 0x00000000
272 MSTPCR1_D: .long 0x00000000
274 REPEAT0_R3: .long 0x00002000
275 REPEAT_R3: .long 0x00000200
276 CS0_A: .long 0xA8000000
278 MIM_U_A: .long 0xFE800008
279 MIM_L_A: .long 0xFE80000C
280 SCR_U_A: .long 0xFE800010
281 SCR_L_A: .long 0xFE800014
282 STR_U_A: .long 0xFE800018
283 STR_L_A: .long 0xFE80001C
284 SDR_U_A: .long 0xFE800030
285 SDR_L_A: .long 0xFE800034
286 EMRS_A: .long 0xFE902000
287 MRS1_A: .long 0xFE900B08
288 MRS2_A: .long 0xFE900308
290 MIM_U_D: .long 0x00000000
291 MIM_L_D0: .long 0x04100008
292 MIM_L_D1: .long 0x02EE0009
293 MIM_L_D2: .long 0x02EE0209
295 SDR_L_A_D0: .long 0x00000300
296 STR_L_A_D0: .long 0x00010040
297 MIM_L_A_D1: .long 0x04100009
298 SCR_L_A_D0: .long 0x00000003
299 SCR_L_A_D1: .long 0x00000002
300 MIM_L_A_D2: .long 0x04100209
301 SCR_L_A_D2: .long 0x00000004
303 SCR_L_NORMAL: .long 0x00000000
304 SCR_L_NOP: .long 0x00000001
305 SCR_L_PALL: .long 0x00000002
306 SCR_L_CKE_EN: .long 0x00000003
307 SCR_L_CBR: .long 0x00000004
309 STR_L_D: .long 0x000F3980
310 SDR_L_D: .long 0x00000400
311 EMRS_D: .long 0x00000000
312 MRS1_D: .long 0x00000000
313 MRS2_D: .long 0x00000000
316 USB_USBHSC_A: .long 0xFFEC80F0
317 USB_USBHSC_D: .long 0x00000000