board/esg/ima3-mx53/ima3-mx53.c

   1 /*
   2  * (C) Copyright 2012, Stefano Babic <sbabic@denx.de>
   3  *
   4  * (C) Copyright 2010 Freescale Semiconductor, Inc.
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc.
  22  */
  23 #include <common.h>
  24 #include <asm/io.h>
  25 #include <asm/arch/imx-regs.h>
  26 #include <asm/arch/mx5x_pins.h>
  27 #include <asm/arch/sys_proto.h>
  28 #include <asm/arch/crm_regs.h>
  29 #include <asm/arch/clock.h>
  30 #include <asm/arch/iomux.h>
  31 #include <asm/errno.h>
  32 #include <netdev.h>
  33 #include <mmc.h>
  34 #include <fsl_esdhc.h>
  35 #include <asm/gpio.h>
  36
  37 /* NOR flash configuration */
  38 #define IMA3_MX53_CS0GCR1       (CSEN | DSZ(2))
  39 #define IMA3_MX53_CS0GCR2       0
  40 #define IMA3_MX53_CS0RCR1       (RCSN(2) | OEN(1) | RWSC(15))
  41 #define IMA3_MX53_CS0RCR2       0
  42 #define IMA3_MX53_CS0WCR1       (WBED1 | WCSN(2) | WEN(1) | WWSC(15))
  43 #define IMA3_MX53_CS0WCR2       0
  44
  45 DECLARE_GLOBAL_DATA_PTR;
  46
  47 static void weim_nor_settings(void)
  48 {
  49         struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
  50
  51         writel(IMA3_MX53_CS0GCR1, &weim_regs->cs0gcr1);
  52         writel(IMA3_MX53_CS0GCR2, &weim_regs->cs0gcr2);
  53         writel(IMA3_MX53_CS0RCR1, &weim_regs->cs0rcr1);
  54         writel(IMA3_MX53_CS0RCR2, &weim_regs->cs0rcr2);
  55         writel(IMA3_MX53_CS0WCR1, &weim_regs->cs0wcr1);
  56         writel(IMA3_MX53_CS0WCR2, &weim_regs->cs0wcr2);
  57         writel(0x0, &weim_regs->wcr);
  58
  59         set_chipselect_size(CS0_128);
  60 }
  61
  62 int dram_init(void)
  63 {
  64         gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
  65                         PHYS_SDRAM_1_SIZE);
  66         return 0;
  67 }
  68
  69 static void setup_iomux_uart(void)
  70 {
  71         /* UART4 RXD */
  72         mxc_request_iomux(MX53_PIN_CSI0_D13, IOMUX_CONFIG_ALT2);
  73         mxc_iomux_set_pad(MX53_PIN_CSI0_D13,
  74                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
  75                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE |
  76                 PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
  77         mxc_iomux_set_input(MX53_UART4_IPP_UART_RXD_MUX_SELECT_INPUT, 0x3);
  78
  79         /* UART4 TXD */
  80         mxc_request_iomux(MX53_PIN_CSI0_D12, IOMUX_CONFIG_ALT2);
  81         mxc_iomux_set_pad(MX53_PIN_CSI0_D12,
  82                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
  83                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE |
  84                 PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
  85 }
  86
  87 static void setup_iomux_fec(void)
  88 {
  89         /*FEC_MDIO*/
  90         mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
  91         mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
  92                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
  93                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_22K_PU |
  94                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
  95         mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
  96
  97         /*FEC_MDC*/
  98         mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
  99         mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
 100
 101         /* FEC RXD3 */
 102         mxc_request_iomux(MX53_PIN_KEY_COL0, IOMUX_CONFIG_ALT6);
 103         mxc_iomux_set_pad(MX53_PIN_KEY_COL0, PAD_CTL_HYS_ENABLE |
 104                 PAD_CTL_PKE_ENABLE);
 105
 106         /* FEC RXD2 */
 107         mxc_request_iomux(MX53_PIN_KEY_COL2, IOMUX_CONFIG_ALT6);
 108         mxc_iomux_set_pad(MX53_PIN_KEY_COL2, PAD_CTL_HYS_ENABLE |
 109                 PAD_CTL_PKE_ENABLE);
 110
 111         /* FEC RXD1 */
 112         mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
 113         mxc_iomux_set_pad(MX53_PIN_FEC_RXD1, PAD_CTL_HYS_ENABLE |
 114                 PAD_CTL_PKE_ENABLE);
 115
 116         /* FEC RXD0 */
 117         mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
 118         mxc_iomux_set_pad(MX53_PIN_FEC_RXD0, PAD_CTL_HYS_ENABLE |
 119                 PAD_CTL_PKE_ENABLE);
 120
 121         /* FEC TXD3 */
 122         mxc_request_iomux(MX53_PIN_GPIO_19, IOMUX_CONFIG_ALT6);
 123         mxc_iomux_set_pad(MX53_PIN_GPIO_19, PAD_CTL_DRV_HIGH);
 124
 125         /* FEC TXD2 */
 126         mxc_request_iomux(MX53_PIN_KEY_ROW2, IOMUX_CONFIG_ALT6);
 127         mxc_iomux_set_pad(MX53_PIN_KEY_ROW2, PAD_CTL_DRV_HIGH);
 128
 129         /* FEC TXD1 */
 130         mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
 131         mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
 132
 133         /* FEC TXD0 */
 134         mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
 135         mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
 136
 137         /* FEC TX_EN */
 138         mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
 139         mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
 140
 141         /* FEC TX_CLK */
 142         mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
 143         mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK, PAD_CTL_HYS_ENABLE |
 144                 PAD_CTL_PKE_ENABLE);
 145
 146         /* FEC RX_ER */
 147         mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
 148         mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER, PAD_CTL_HYS_ENABLE |
 149                 PAD_CTL_PKE_ENABLE);
 150
 151         /* FEC RX_DV */
 152         mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
 153         mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV, PAD_CTL_HYS_ENABLE |
 154                 PAD_CTL_PKE_ENABLE);
 155
 156         /* FEC CRS */
 157         mxc_request_iomux(MX53_PIN_KEY_COL3, IOMUX_CONFIG_ALT6);
 158         mxc_iomux_set_pad(MX53_PIN_KEY_COL3, PAD_CTL_HYS_ENABLE |
 159                 PAD_CTL_PKE_ENABLE);
 160
 161         /* FEC COL */
 162         mxc_request_iomux(MX53_PIN_KEY_ROW1, IOMUX_CONFIG_ALT6);
 163         mxc_iomux_set_pad(MX53_PIN_KEY_ROW1, PAD_CTL_HYS_ENABLE |
 164                 PAD_CTL_PKE_ENABLE);
 165         mxc_iomux_set_input(MX53_FEC_FEC_COL_SELECT_INPUT, 0x0);
 166
 167         /* FEC RX_CLK */
 168         mxc_request_iomux(MX53_PIN_KEY_COL1, IOMUX_CONFIG_ALT6);
 169         mxc_iomux_set_pad(MX53_PIN_KEY_COL1, PAD_CTL_HYS_ENABLE |
 170                 PAD_CTL_PKE_ENABLE);
 171         mxc_iomux_set_input(MX53_FEC_FEC_RX_CLK_SELECT_INPUT, 0x0);
 172 }
 173
 174 #ifdef CONFIG_FSL_ESDHC
 175 struct fsl_esdhc_cfg esdhc_cfg = { MMC_SDHC1_BASE_ADDR };
 176
 177 int board_mmc_getcd(struct mmc *mmc)
 178 {
 179         int ret;
 180
 181         ret = !gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_1));
 182
 183         return ret;
 184 }
 185
 186 int board_mmc_init(bd_t *bis)
 187 {
 188         mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
 189         mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
 190         mxc_request_iomux(MX53_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);
 191         mxc_request_iomux(MX53_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);
 192         mxc_request_iomux(MX53_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0);
 193         mxc_request_iomux(MX53_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0);
 194         mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1);
 195         mxc_iomux_set_pad(MX53_PIN_GPIO_1,
 196                 PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
 197                 PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU |
 198                 PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_PKE_ENABLE);
 199         gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_GPIO_1));
 200
 201         mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
 202                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
 203                 PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
 204         mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
 205                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE |
 206                 PAD_CTL_47K_PU | PAD_CTL_DRV_HIGH);
 207         mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
 208                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
 209                 PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 210         mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
 211                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
 212                 PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 213         mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
 214                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
 215                 PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 216         mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
 217                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
 218                 PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 219
 220         esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 221         return fsl_esdhc_initialize(bis, &esdhc_cfg);
 222 }
 223 #endif
 224
 225 static void setup_iomux_spi(void)
 226 {
 227         /* SCLK */
 228         mxc_request_iomux(MX53_PIN_CSI0_D8, IOMUX_CONFIG_ALT3);
 229         mxc_iomux_set_pad(MX53_PIN_CSI0_D8,
 230                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
 231                 PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 232         mxc_iomux_set_input(MX53_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT, 0x1);
 233         /* MOSI */
 234         mxc_request_iomux(MX53_PIN_CSI0_D9, IOMUX_CONFIG_ALT3);
 235         mxc_iomux_set_pad(MX53_PIN_CSI0_D9,
 236                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
 237                 PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 238         mxc_iomux_set_input(MX53_ECSPI2_IPP_IND_MOSI_SELECT_INPUT, 0x1);
 239         /* MISO */
 240         mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT3);
 241         mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
 242                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
 243                 PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 244         mxc_iomux_set_input(MX53_ECSPI2_IPP_IND_MISO_SELECT_INPUT, 0x1);
 245         /* SSEL 0 */
 246         mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_GPIO);
 247         mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
 248                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
 249                 PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 250         gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_CSI0_D11), 1);
 251 }
 252
 253 int board_early_init_f(void)
 254 {
 255         /* configure I/O pads */
 256         setup_iomux_uart();
 257         setup_iomux_fec();
 258
 259         weim_nor_settings();
 260
 261         /* configure spi */
 262         setup_iomux_spi();
 263
 264         return 0;
 265 }
 266
 267 int board_init(void)
 268 {
 269         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 270
 271         mxc_set_sata_internal_clock();
 272
 273         return 0;
 274 }
 275
 276 #if defined(CONFIG_RESET_PHY_R)
 277 #include <miiphy.h>
 278
 279 void reset_phy(void)
 280 {
 281         unsigned short reg;
 282
 283         /* reset the phy */
 284         miiphy_reset("FEC", CONFIG_PHY_ADDR);
 285
 286         /* set hard link to 100Mbit, full-duplex */
 287         miiphy_read("FEC", CONFIG_PHY_ADDR, MII_BMCR, &reg);
 288         reg &= ~BMCR_ANENABLE;
 289         reg |= (BMCR_SPEED100 | BMCR_FULLDPLX);
 290         miiphy_write("FEC", CONFIG_PHY_ADDR, MII_BMCR, reg);
 291
 292         miiphy_read("FEC", CONFIG_PHY_ADDR, 0x16, &reg);
 293         reg |= (1 << 5);
 294         miiphy_write("FEC", CONFIG_PHY_ADDR, 0x16, reg);
 295 }
 296 #endif
 297
 298 int checkboard(void)
 299 {
 300         puts("Board: IMA3_MX53\n");
 301
 302         return 0;
 303 }