board/esd/voh405/voh405.c

   1 /*
   2  * (C) Copyright 2001-2004
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <asm/io.h>
  26 #include <asm/processor.h>
  27 #include <command.h>
  28 #include <malloc.h>
  29
  30 /* ------------------------------------------------------------------------- */
  31
  32 #if 0
  33 #define FPGA_DEBUG
  34 #endif
  35
  36 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
  37 extern void lxt971_no_sleep(void);
  38
  39 /* fpga configuration data - gzip compressed and generated by bin2c */
  40 const unsigned char fpgadata[] =
  41 {
  42 #include "fpgadata.c"
  43 };
  44
  45 /*
  46  * include common fpga code (for esd boards)
  47  */
  48 #include "../common/fpga.c"
  49
  50
  51 /* Prototypes */
  52 int gunzip(void *, int, unsigned char *, unsigned long *);
  53
  54
  55 /* logo bitmap data - gzip compressed and generated by bin2c */
  56 unsigned char logo_bmp_320[] =
  57 {
  58 #include "logo_320_240_4bpp.c"
  59 };
  60
  61 unsigned char logo_bmp_640[] =
  62 {
  63 #include "logo_640_480_24bpp.c"
  64 };
  65
  66
  67 /*
  68  * include common lcd code (for esd boards)
  69  */
  70 #include "../common/lcd.c"
  71
  72 #include "../common/s1d13704_320_240_4bpp.h"
  73 #include "../common/s1d13806_320_240_4bpp.h"
  74 #include "../common/s1d13806_640_480_16bpp.h"
  75
  76
  77 int board_early_init_f (void)
  78 {
  79         /*
  80          * IRQ 0-15  405GP internally generated; active high; level sensitive
  81          * IRQ 16    405GP internally generated; active low; level sensitive
  82          * IRQ 17-24 RESERVED
  83          * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
  84          * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
  85          * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
  86          * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
  87          * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
  88          * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
  89          * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
  90          */
  91         mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
  92         mtdcr(uicer, 0x00000000);       /* disable all ints */
  93         mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
  94         mtdcr(uicpr, 0xFFFFFFB5);       /* set int polarities */
  95         mtdcr(uictr, 0x10000000);       /* set int trigger levels */
  96         mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
  97         mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
  98
  99         /*
 100          * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
 101          */
 102         mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
 103
 104         return 0;
 105 }
 106
 107 int misc_init_r (void)
 108 {
 109         unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
 110         unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
 111         unsigned short *lcd_contrast =
 112                 (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 4);
 113         unsigned short *lcd_backlight =
 114                 (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 6);
 115         unsigned char *dst;
 116         ulong len = sizeof(fpgadata);
 117         int status;
 118         int index;
 119         int i;
 120         char *str;
 121
 122         dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
 123         if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
 124                 printf ("GUNZIP ERROR - must RESET board to recover\n");
 125                 do_reset (NULL, 0, 0, NULL);
 126         }
 127
 128         status = fpga_boot(dst, len);
 129         if (status != 0) {
 130                 printf("\nFPGA: Booting failed ");
 131                 switch (status) {
 132                 case ERROR_FPGA_PRG_INIT_LOW:
 133                         printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
 134                         break;
 135                 case ERROR_FPGA_PRG_INIT_HIGH:
 136                         printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
 137                         break;
 138                 case ERROR_FPGA_PRG_DONE:
 139                         printf("(Timeout: DONE not high after programming FPGA)\n ");
 140                         break;
 141                 }
 142
 143                 /* display infos on fpgaimage */
 144                 index = 15;
 145                 for (i=0; i<4; i++) {
 146                         len = dst[index];
 147                         printf("FPGA: %s\n", &(dst[index+1]));
 148                         index += len+3;
 149                 }
 150                 putc ('\n');
 151                 /* delayed reboot */
 152                 for (i=20; i>0; i--) {
 153                         printf("Rebooting in %2d seconds \r",i);
 154                         for (index=0;index<1000;index++)
 155                                 udelay(1000);
 156                 }
 157                 putc ('\n');
 158                 do_reset(NULL, 0, 0, NULL);
 159         }
 160
 161         puts("FPGA:  ");
 162
 163         /* display infos on fpgaimage */
 164         index = 15;
 165         for (i=0; i<4; i++) {
 166                 len = dst[index];
 167                 printf("%s ", &(dst[index+1]));
 168                 index += len+3;
 169         }
 170         putc ('\n');
 171
 172         free(dst);
 173
 174         /*
 175          * Reset FPGA via FPGA_INIT pin
 176          */
 177         out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | FPGA_INIT); /* setup FPGA_INIT as output */
 178         out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~FPGA_INIT);  /* reset low */
 179         udelay(1000); /* wait 1ms */
 180         out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | FPGA_INIT);   /* reset high */
 181         udelay(1000); /* wait 1ms */
 182
 183         /*
 184          * Reset external DUARTs
 185          */
 186         out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_DUART_RST); /* set reset to high */
 187         udelay(10); /* wait 10us */
 188         out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_DUART_RST); /* set reset to low */
 189         udelay(1000); /* wait 1ms */
 190
 191         /*
 192          * Set NAND-FLASH GPIO signals to default
 193          */
 194         out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
 195         out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_NAND_CE);
 196
 197         /*
 198          * Setup EEPROM write protection
 199          */
 200         out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
 201         out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CONFIG_SYS_EEPROM_WP);
 202
 203         /*
 204          * Enable interrupts in exar duart mcr[3]
 205          */
 206         out_8(duart0_mcr, 0x08);
 207         out_8(duart1_mcr, 0x08);
 208
 209         /*
 210          * Init lcd interface and display logo
 211          */
 212         str = getenv("bd_type");
 213         if (strcmp(str, "voh405_bw") == 0) {
 214                 lcd_setup(0, 1);
 215                 lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
 216                          regs_13704_320_240_4bpp,
 217                          sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
 218                          logo_bmp_320, sizeof(logo_bmp_320));
 219         } else if (strcmp(str, "voh405_bwbw") == 0) {
 220                 lcd_setup(0, 1);
 221                 lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
 222                          regs_13704_320_240_4bpp,
 223                          sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
 224                          logo_bmp_320, sizeof(logo_bmp_320));
 225                 lcd_setup(1, 1);
 226                 lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
 227                          regs_13806_320_240_4bpp,
 228                          sizeof(regs_13806_320_240_4bpp)/sizeof(regs_13806_320_240_4bpp[0]),
 229                          logo_bmp_320, sizeof(logo_bmp_320));
 230         } else if (strcmp(str, "voh405_bwc") == 0) {
 231                 lcd_setup(0, 1);
 232                 lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
 233                          regs_13704_320_240_4bpp,
 234                          sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
 235                          logo_bmp_320, sizeof(logo_bmp_320));
 236                 lcd_setup(1, 0);
 237                 lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
 238                          regs_13806_640_480_16bpp,
 239                          sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]),
 240                          logo_bmp_640, sizeof(logo_bmp_640));
 241         } else {
 242                 printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
 243                 return 0;
 244         }
 245
 246         /*
 247          * Set invert bit in small lcd controller
 248          */
 249         out_8((unsigned char *)(CONFIG_SYS_LCD_SMALL_REG + 2),
 250               in_8((unsigned char *)(CONFIG_SYS_LCD_SMALL_REG + 2)) | 0x01);
 251
 252         /*
 253          * Set default contrast voltage on epson vga controller
 254          */
 255         out_be16(lcd_contrast, 0x4646);
 256
 257         /*
 258          * Enable backlight
 259          */
 260         out_be16(lcd_backlight, 0xffff);
 261
 262         /*
 263          * Enable external I2C bus
 264          */
 265         out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CONFIG_SYS_IIC_ON);
 266
 267         return (0);
 268 }
 269
 270
 271 /*
 272  * Check Board Identity:
 273  */
 274
 275 int checkboard (void)
 276 {
 277         char str[64];
 278         int i = getenv_r ("serial#", str, sizeof(str));
 279
 280         puts ("Board: ");
 281
 282         if (i == -1) {
 283                 puts ("### No HW ID - assuming VOH405");
 284         } else {
 285                 puts(str);
 286         }
 287
 288         if (getenv_r("bd_type", str, sizeof(str)) != -1) {
 289                 printf(" (%s)", str);
 290         } else {
 291                 puts(" (Missing bd_type!)");
 292         }
 293
 294         putc ('\n');
 295
 296         return 0;
 297 }
 298
 299 #ifdef CONFIG_IDE_RESET
 300 #define FPGA_MODE (CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL)
 301 void ide_set_reset(int on)
 302 {
 303         /*
 304          * Assert or deassert CompactFlash Reset Pin
 305          */
 306         if (on) {               /* assert RESET */
 307                 out_be16((void *)FPGA_MODE,
 308                          in_be16((void *)FPGA_MODE) & ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
 309         } else {                /* release RESET */
 310                 out_be16((void *)FPGA_MODE,
 311                          in_be16((void *)FPGA_MODE) | CONFIG_SYS_FPGA_CTRL_CF_RESET);
 312         }
 313 }
 314 #endif /* CONFIG_IDE_RESET */
 315
 316 #if defined(CONFIG_RESET_PHY_R)
 317 void reset_phy(void)
 318 {
 319 #ifdef CONFIG_LXT971_NO_SLEEP
 320
 321         /*
 322          * Disable sleep mode in LXT971
 323          */
 324         lxt971_no_sleep();
 325 #endif
 326 }
 327 #endif
 328
 329 #if defined(CONFIG_SYS_EEPROM_WREN)
 330 /* Input: <dev_addr>  I2C address of EEPROM device to enable.
 331  *         <state>     -1: deliver current state
 332  *                     0: disable write
 333  *                     1: enable write
 334  *  Returns:           -1: wrong device address
 335  *                      0: dis-/en- able done
 336  *                   0/1: current state if <state> was -1.
 337  */
 338 int eeprom_write_enable (unsigned dev_addr, int state)
 339 {
 340         if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
 341                 return -1;
 342         } else {
 343                 switch (state) {
 344                 case 1:
 345                         /* Enable write access, clear bit GPIO0. */
 346                         out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
 347                         state = 0;
 348                         break;
 349                 case 0:
 350                         /* Disable write access, set bit GPIO0. */
 351                         out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
 352                         state = 0;
 353                         break;
 354                 default:
 355                         /* Read current status back. */
 356                         state = (0 == (in_be32((void*)GPIO0_OR) & CONFIG_SYS_EEPROM_WP));
 357                         break;
 358                 }
 359         }
 360         return state;
 361 }
 362
 363 int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 364 {
 365         int query = argc == 1;
 366         int state = 0;
 367
 368         if (query) {
 369                 /* Query write access state. */
 370                 state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
 371                 if (state < 0) {
 372                         puts ("Query of write access state failed.\n");
 373                 } else {
 374                         printf ("Write access for device 0x%0x is %sabled.\n",
 375                                 CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
 376                         state = 0;
 377                 }
 378         } else {
 379                 if ('0' == argv[1][0]) {
 380                         /* Disable write access. */
 381                         state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
 382                 } else {
 383                         /* Enable write access. */
 384                         state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
 385                 }
 386                 if (state < 0) {
 387                         puts ("Setup of write access state failed.\n");
 388                 }
 389         }
 390
 391         return state;
 392 }
 393
 394 U_BOOT_CMD(eepwren,     2,      0,      do_eep_wren,
 395         "Enable / disable / query EEPROM write access",
 396         ""
 397 );
 398 #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */