board/esd/pmc440/pmc440.c

   1 /*
   2  * (C) Copyright 2007
   3  * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
   4  * Based on board/amcc/sequoia/sequoia.c
   5  *
   6  * (C) Copyright 2006
   7  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   8  *
   9  * (C) Copyright 2006
  10  * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
  11  * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 #include <common.h>
  30 #include <libfdt.h>
  31 #include <fdt_support.h>
  32 #include <ppc440.h>
  33 #include <asm/processor.h>
  34 #include <asm/io.h>
  35 #include <command.h>
  36 #include <i2c.h>
  37 #ifdef CONFIG_RESET_PHY_R
  38 #include <miiphy.h>
  39 #endif
  40 #include <serial.h>
  41 #include "fpga.h"
  42 #include "pmc440.h"
  43
  44 DECLARE_GLOBAL_DATA_PTR;
  45
  46 extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips    */
  47
  48 ulong flash_get_size(ulong base, int banknum);
  49 int pci_is_66mhz(void);
  50 int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt);
  51
  52
  53 struct serial_device *default_serial_console(void)
  54 {
  55         uchar buf[4];
  56         ulong delay;
  57         int i;
  58         ulong val;
  59
  60         /*
  61          * Use default console on P4 when strapping jumper
  62          * is installed (bootstrap option != 'H').
  63          */
  64         mfsdr(SDR_PINSTP, val);
  65         if (((val & 0xf0000000) >> 29) != 7)
  66                 return &serial1_device;
  67
  68         ulong scratchreg = in_be32((void*)GPIO0_ISR3L);
  69         if (!(scratchreg & 0x80)) {
  70                 /* mark scratchreg valid */
  71                 scratchreg = (scratchreg & 0xffffff00) | 0x80;
  72
  73                 i = bootstrap_eeprom_read(CFG_I2C_BOOT_EEPROM_ADDR, 0x10, buf, 4);
  74                 if ((i != -1) && (buf[0] == 0x19) && (buf[1] == 0x75)) {
  75                         scratchreg |= buf[2];
  76
  77                         /* bringup delay for console */
  78                         for (delay=0; delay<(1000 * (ulong)buf[3]); delay++) {
  79                                 udelay(1000);
  80                         }
  81                 } else
  82                         scratchreg |= 0x01;
  83                 out_be32((void*)GPIO0_ISR3L, scratchreg);
  84         }
  85
  86         if (scratchreg & 0x01)
  87                 return &serial1_device;
  88         else
  89                 return &serial0_device;
  90 }
  91
  92 int board_early_init_f(void)
  93 {
  94         u32 sdr0_cust0;
  95         u32 sdr0_pfc1, sdr0_pfc2;
  96         u32 reg;
  97
  98         /* general EBC configuration (disable EBC timeouts) */
  99         mtdcr(ebccfga, xbcfg);
 100         mtdcr(ebccfgd, 0xf8400000);
 101
 102         /*--------------------------------------------------------------------
 103          * Setup the GPIO pins
 104          * TODO: setup GPIOs via CFG_4xx_GPIO_TABLE in board's config file
 105          *-------------------------------------------------------------------*/
 106         out32(GPIO0_OR,    0x40000002);
 107         out32(GPIO0_TCR,   0x4c90011f);
 108         out32(GPIO0_OSRL,  0x28011400);
 109         out32(GPIO0_OSRH,  0x55005000);
 110         out32(GPIO0_TSRL,  0x08011400);
 111         out32(GPIO0_TSRH,  0x55005000);
 112         out32(GPIO0_ISR1L, 0x54000000);
 113         out32(GPIO0_ISR1H, 0x00000000);
 114         out32(GPIO0_ISR2L, 0x44000000);
 115         out32(GPIO0_ISR2H, 0x00000100);
 116         out32(GPIO0_ISR3L, 0x00000000);
 117         out32(GPIO0_ISR3H, 0x00000000);
 118
 119         out32(GPIO1_OR,    0x80002408);
 120         out32(GPIO1_TCR,   0xd6003c08);
 121         out32(GPIO1_OSRL,  0x0a5a0000);
 122         out32(GPIO1_OSRH,  0x00000000);
 123         out32(GPIO1_TSRL,  0x00000000);
 124         out32(GPIO1_TSRH,  0x00000000);
 125         out32(GPIO1_ISR1L, 0x00005555);
 126         out32(GPIO1_ISR1H, 0x40000000);
 127         out32(GPIO1_ISR2L, 0x04010000);
 128         out32(GPIO1_ISR2H, 0x00000000);
 129         out32(GPIO1_ISR3L, 0x01400000);
 130         out32(GPIO1_ISR3H, 0x00000000);
 131
 132         /* patch PLB:PCI divider for 66MHz PCI */
 133         mfcpr(clk_spcid, reg);
 134         if (pci_is_66mhz() && (reg != 0x02000000)) {
 135                 mtcpr(clk_spcid, 0x02000000); /* 133MHZ : 2 for 66MHz PCI */
 136
 137                 mfcpr(clk_icfg, reg);
 138                 reg |= CPR0_ICFG_RLI_MASK;
 139                 mtcpr(clk_icfg, reg);
 140
 141                 mtspr(dbcr0, 0x20000000); /* do chip reset */
 142         }
 143
 144         /*--------------------------------------------------------------------
 145          * Setup the interrupt controller polarities, triggers, etc.
 146          *-------------------------------------------------------------------*/
 147         mtdcr(uic0sr, 0xffffffff);      /* clear all */
 148         mtdcr(uic0er, 0x00000000);      /* disable all */
 149         mtdcr(uic0cr, 0x00000005);      /* ATI & UIC1 crit are critical */
 150         mtdcr(uic0pr, 0xfffff7ef);
 151         mtdcr(uic0tr, 0x00000000);
 152         mtdcr(uic0vr, 0x00000000);      /* int31 highest, base=0x000 */
 153         mtdcr(uic0sr, 0xffffffff);      /* clear all */
 154
 155         mtdcr(uic1sr, 0xffffffff);      /* clear all */
 156         mtdcr(uic1er, 0x00000000);      /* disable all */
 157         mtdcr(uic1cr, 0x00000000);      /* all non-critical */
 158         mtdcr(uic1pr, 0xffffc7f5);
 159         mtdcr(uic1tr, 0x00000000);
 160         mtdcr(uic1vr, 0x00000000);      /* int31 highest, base=0x000 */
 161         mtdcr(uic1sr, 0xffffffff);      /* clear all */
 162
 163         mtdcr(uic2sr, 0xffffffff);      /* clear all */
 164         mtdcr(uic2er, 0x00000000);      /* disable all */
 165         mtdcr(uic2cr, 0x00000000);      /* all non-critical */
 166         mtdcr(uic2pr, 0x27ffffff);
 167         mtdcr(uic2tr, 0x00000000);
 168         mtdcr(uic2vr, 0x00000000);      /* int31 highest, base=0x000 */
 169         mtdcr(uic2sr, 0xffffffff);      /* clear all */
 170
 171         /* select Ethernet pins */
 172         mfsdr(SDR0_PFC1, sdr0_pfc1);
 173         sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | SDR0_PFC1_SELECT_CONFIG_4;
 174         mfsdr(SDR0_PFC2, sdr0_pfc2);
 175         sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | SDR0_PFC2_SELECT_CONFIG_4;
 176
 177         /* enable 2nd IIC */
 178         sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
 179
 180         mtsdr(SDR0_PFC2, sdr0_pfc2);
 181         mtsdr(SDR0_PFC1, sdr0_pfc1);
 182
 183         /* setup NAND FLASH */
 184         mfsdr(SDR0_CUST0, sdr0_cust0);
 185         sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL    |
 186                 SDR0_CUST0_NDFC_ENABLE          |
 187                 SDR0_CUST0_NDFC_BW_8_BIT        |
 188                 SDR0_CUST0_NDFC_ARE_MASK        |
 189                 (0x80000000 >> (28 + CFG_NAND_CS));
 190         mtsdr(SDR0_CUST0, sdr0_cust0);
 191
 192         return 0;
 193 }
 194
 195 /*---------------------------------------------------------------------------+
 196   | misc_init_r.
 197   +---------------------------------------------------------------------------*/
 198 int misc_init_r(void)
 199 {
 200         uint pbcr;
 201         int size_val = 0;
 202         u32 reg;
 203         unsigned long usb2d0cr = 0;
 204         unsigned long usb2phy0cr, usb2h0cr = 0;
 205         unsigned long sdr0_pfc1;
 206         char *act = getenv("usbact");
 207
 208         /*
 209          * FLASH stuff...
 210          */
 211
 212         /* Re-do sizing to get full correct info */
 213
 214         /* adjust flash start and offset */
 215         gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 216         gd->bd->bi_flashoffset = 0;
 217
 218 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
 219         mtdcr(ebccfga, pb2cr);
 220 #else
 221         mtdcr(ebccfga, pb0cr);
 222 #endif
 223         pbcr = mfdcr(ebccfgd);
 224         switch (gd->bd->bi_flashsize) {
 225         case 1 << 20:
 226                 size_val = 0;
 227                 break;
 228         case 2 << 20:
 229                 size_val = 1;
 230                 break;
 231         case 4 << 20:
 232                 size_val = 2;
 233                 break;
 234         case 8 << 20:
 235                 size_val = 3;
 236                 break;
 237         case 16 << 20:
 238                 size_val = 4;
 239                 break;
 240         case 32 << 20:
 241                 size_val = 5;
 242                 break;
 243         case 64 << 20:
 244                 size_val = 6;
 245                 break;
 246         case 128 << 20:
 247                 size_val = 7;
 248                 break;
 249         }
 250         pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
 251 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
 252         mtdcr(ebccfga, pb2cr);
 253 #else
 254         mtdcr(ebccfga, pb0cr);
 255 #endif
 256         mtdcr(ebccfgd, pbcr);
 257
 258         /*
 259          * Re-check to get correct base address
 260          */
 261         flash_get_size(gd->bd->bi_flashstart, 0);
 262
 263 #ifdef CFG_ENV_IS_IN_FLASH
 264         /* Monitor protection ON by default */
 265         (void)flash_protect(FLAG_PROTECT_SET,
 266                             -CFG_MONITOR_LEN,
 267                             0xffffffff,
 268                             &flash_info[0]);
 269
 270         /* Env protection ON by default */
 271         (void)flash_protect(FLAG_PROTECT_SET,
 272                             CFG_ENV_ADDR_REDUND,
 273                             CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
 274                             &flash_info[0]);
 275 #endif
 276
 277         /*
 278          * USB suff...
 279          */
 280         if ((act == NULL || strcmp(act, "hostdev") == 0) &&
 281             !(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)){
 282                 /* SDR Setting */
 283                 mfsdr(SDR0_PFC1, sdr0_pfc1);
 284                 mfsdr(SDR0_USB2D0CR, usb2d0cr);
 285                 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 286                 mfsdr(SDR0_USB2H0CR, usb2h0cr);
 287
 288                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
 289                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;       /*0*/
 290                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
 291                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;    /*1*/
 292                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
 293                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;         /*0*/
 294                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
 295                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;          /*1*/
 296                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
 297                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;          /*1*/
 298
 299                 /* An 8-bit/60MHz interface is the only possible alternative
 300                    when connecting the Device to the PHY */
 301                 usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
 302                 usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;        /*1*/
 303
 304                 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
 305                 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
 306
 307                 mtsdr(SDR0_PFC1, sdr0_pfc1);
 308                 mtsdr(SDR0_USB2D0CR, usb2d0cr);
 309                 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 310                 mtsdr(SDR0_USB2H0CR, usb2h0cr);
 311
 312                 /*clear resets*/
 313                 udelay(1000);
 314                 mtsdr(SDR0_SRST1, 0x00000000);
 315                 udelay(1000);
 316                 mtsdr(SDR0_SRST0, 0x00000000);
 317
 318                 printf("USB:   Host\n");
 319
 320         } else if ((strcmp(act, "dev") == 0) || (in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) {
 321                 /*-------------------PATCH-------------------------------*/
 322                 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 323
 324                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
 325                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;       /*0*/
 326                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
 327                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;         /*0*/
 328                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
 329                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;          /*1*/
 330                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
 331                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;          /*1*/
 332                 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 333
 334                 udelay (1000);
 335                 mtsdr(SDR0_SRST1, 0x672c6000);
 336
 337                 udelay (1000);
 338                 mtsdr(SDR0_SRST0, 0x00000080);
 339
 340                 udelay (1000);
 341                 mtsdr(SDR0_SRST1, 0x60206000);
 342
 343                 *(unsigned int *)(0xe0000350) = 0x00000001;
 344
 345                 udelay (1000);
 346                 mtsdr(SDR0_SRST1, 0x60306000);
 347                 /*-------------------PATCH-------------------------------*/
 348
 349                 /* SDR Setting */
 350                 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 351                 mfsdr(SDR0_USB2H0CR, usb2h0cr);
 352                 mfsdr(SDR0_USB2D0CR, usb2d0cr);
 353                 mfsdr(SDR0_PFC1, sdr0_pfc1);
 354
 355                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
 356                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;       /*0*/
 357                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
 358                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;     /*0*/
 359                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
 360                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;          /*1*/
 361                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
 362                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;           /*0*/
 363                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
 364                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;           /*0*/
 365
 366                 usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
 367                 usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;         /*0*/
 368
 369                 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
 370
 371                 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
 372                 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;                /*1*/
 373
 374                 mtsdr(SDR0_USB2H0CR, usb2h0cr);
 375                 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 376                 mtsdr(SDR0_USB2D0CR, usb2d0cr);
 377                 mtsdr(SDR0_PFC1, sdr0_pfc1);
 378
 379                 /*clear resets*/
 380                 udelay(1000);
 381                 mtsdr(SDR0_SRST1, 0x00000000);
 382                 udelay(1000);
 383                 mtsdr(SDR0_SRST0, 0x00000000);
 384
 385                 printf("USB:   Device\n");
 386         }
 387
 388         /*
 389          * Clear PLB4A0_ACR[WRP]
 390          * This fix will make the MAL burst disabling patch for the Linux
 391          * EMAC driver obsolete.
 392          */
 393         reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
 394         mtdcr(plb4_acr, reg);
 395
 396 #ifdef CONFIG_FPGA
 397         pmc440_init_fpga();
 398 #endif
 399
 400         /* turn off POST LED */
 401         out_be32((void*)GPIO1_OR,  in_be32((void*)GPIO1_OR) & ~GPIO1_POST_N);
 402         /* turn on RUN LED */
 403         out_be32((void*)GPIO0_OR,  in_be32((void*)GPIO0_OR) & ~GPIO0_LED_RUN_N);
 404         return 0;
 405 }
 406
 407 int is_monarch(void)
 408 {
 409         if (in_be32((void*)GPIO1_IR) & GPIO1_NONMONARCH)
 410                 return 0;
 411
 412         return 1;
 413 }
 414
 415 int pci_is_66mhz(void)
 416 {
 417         if (in_be32((void*)GPIO1_IR) & GPIO1_M66EN)
 418                 return 1;
 419         return 0;
 420 }
 421
 422 int board_revision(void)
 423 {
 424         return (int)((in_be32((void*)GPIO1_IR) & GPIO1_HWID_MASK) >> 4);
 425 }
 426
 427 int checkboard(void)
 428 {
 429         puts("Board: esd GmbH - PMC440");
 430
 431         gd->board_type = board_revision();
 432         printf(", Rev 1.%ld, ", gd->board_type);
 433
 434         if (!is_monarch()) {
 435                 puts("non-");
 436         }
 437
 438         printf("monarch, PCI=%s MHz\n", pci_is_66mhz() ? "66" : "33");
 439         return (0);
 440 }
 441
 442
 443 #if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
 444 /*
 445  * Assign interrupts to PCI devices. Some OSs rely on this.
 446  */
 447 void pmc440_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
 448 {
 449         unsigned char int_line[] = {IRQ_PCIC, IRQ_PCID, IRQ_PCIA, IRQ_PCIB};
 450
 451         pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
 452                                    int_line[PCI_DEV(dev) & 0x03]);
 453 }
 454 #endif
 455
 456 /*************************************************************************
 457  *  pci_pre_init
 458  *
 459  *  This routine is called just prior to registering the hose and gives
 460  *  the board the opportunity to check things. Returning a value of zero
 461  *  indicates that things are bad & PCI initialization should be aborted.
 462  *
 463  *      Different boards may wish to customize the pci controller structure
 464  *      (add regions, override default access routines, etc) or perform
 465  *      certain pre-initialization actions.
 466  *
 467  ************************************************************************/
 468 #if defined(CONFIG_PCI)
 469 int pci_pre_init(struct pci_controller *hose)
 470 {
 471         unsigned long addr;
 472
 473         /*-------------------------------------------------------------------------+
 474           | Set priority for all PLB3 devices to 0.
 475           | Set PLB3 arbiter to fair mode.
 476           +-------------------------------------------------------------------------*/
 477         mfsdr(sdr_amp1, addr);
 478         mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
 479         addr = mfdcr(plb3_acr);
 480         mtdcr(plb3_acr, addr | 0x80000000);
 481
 482         /*-------------------------------------------------------------------------+
 483           | Set priority for all PLB4 devices to 0.
 484           +-------------------------------------------------------------------------*/
 485         mfsdr(sdr_amp0, addr);
 486         mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
 487         addr = mfdcr(plb4_acr) | 0xa0000000;    /* Was 0x8---- */
 488         mtdcr(plb4_acr, addr);
 489
 490         /*-------------------------------------------------------------------------+
 491           | Set Nebula PLB4 arbiter to fair mode.
 492           +-------------------------------------------------------------------------*/
 493         /* Segment0 */
 494         addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
 495         addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
 496         addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
 497         addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
 498         mtdcr(plb0_acr, addr);
 499
 500         /* Segment1 */
 501         addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
 502         addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
 503         addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
 504         addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
 505         mtdcr(plb1_acr, addr);
 506
 507 #ifdef CONFIG_PCI_PNP
 508         hose->fixup_irq = pmc440_pci_fixup_irq;
 509 #endif
 510
 511         return 1;
 512 }
 513 #endif /* defined(CONFIG_PCI) */
 514
 515 /*
 516  * pci_target_init
 517  *
 518  * The bootstrap configuration provides default settings for the pci
 519  * inbound map (PIM). But the bootstrap config choices are limited and
 520  * may not be sufficient for a given board.
 521  */
 522 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 523 void pci_target_init(struct pci_controller *hose)
 524 {
 525         char *ptmla_str, *ptmms_str;
 526
 527         /*
 528          * Set up Direct MMIO registers
 529          */
 530         /*
 531          * PowerPC440EPX PCI Master configuration.
 532          * Map one 1Gig range of PLB/processor addresses to PCI memory space.
 533          * PLB address 0x80000000-0xBFFFFFFF
 534          *     ==> PCI address 0x80000000-0xBFFFFFFF
 535          * Use byte reversed out routines to handle endianess.
 536          * Make this region non-prefetchable.
 537          */
 538         out32r(PCIX0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute */
 539                                                 /* - disabled b4 setting */
 540         out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);  /* PMM0 Local Address */
 541         out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
 542         out32r(PCIX0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
 543         out32r(PCIX0_PMM0MA, 0xc0000001);       /* 1G + No prefetching, */
 544                                                 /* and enable region */
 545
 546         if (!is_monarch()) {
 547                 ptmla_str = getenv("ptm1la");
 548                 ptmms_str = getenv("ptm1ms");
 549                 if(NULL != ptmla_str && NULL != ptmms_str ) {
 550                         out32r(PCIX0_PTM1MS,
 551                                simple_strtoul(ptmms_str, NULL, 16));
 552                         out32r(PCIX0_PTM1LA,
 553                                simple_strtoul(ptmla_str, NULL, 16));
 554                 } else {
 555                         /* BAR1: default top 64MB of RAM */
 556                         out32r(PCIX0_PTM1MS, 0xfc000001);
 557                         out32r(PCIX0_PTM1LA, 0x0c000000);
 558                 }
 559         } else {
 560                 /* BAR1: default: complete 256MB RAM */
 561                 out32r(PCIX0_PTM1MS, 0xf0000001);
 562                 out32r(PCIX0_PTM1LA, 0x00000000);
 563         }
 564
 565         ptmla_str = getenv("ptm2la");           /* Local Addr. Reg */
 566         ptmms_str = getenv("ptm2ms");           /* Memory Size/Attribute */
 567         if(NULL != ptmla_str && NULL != ptmms_str ) {
 568                 out32r(PCIX0_PTM2MS, simple_strtoul(ptmms_str, NULL, 16));
 569                 out32r(PCIX0_PTM2LA, simple_strtoul(ptmla_str, NULL, 16));
 570         } else {
 571                 /* BAR2: default: 16 MB FPGA + registers */
 572                 out32r(PCIX0_PTM2MS, 0xff000001); /* Memory Size/Attribute */
 573                 out32r(PCIX0_PTM2LA, 0xef000000); /* Local Addr. Reg */
 574         }
 575
 576         if (is_monarch()) {
 577                 /* BAR2: map FPGA registers behind system memory at 1GB */
 578                 pci_write_config_dword(0, PCI_BASE_ADDRESS_2, 0x40000008);
 579         }
 580
 581         /*
 582          * Set up Configuration registers
 583          */
 584
 585         /* Program the board's vendor id */
 586         pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
 587                               CFG_PCI_SUBSYS_VENDORID);
 588
 589 #if 0   /* disabled for PMC405 backward compatibility */
 590         /* Configure command register as bus master */
 591         pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
 592 #endif
 593
 594         /* 240nS PCI clock */
 595         pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
 596
 597         /* No error reporting */
 598         pci_write_config_word(0, PCI_ERREN, 0);
 599
 600         pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
 601
 602         if (!is_monarch()) {
 603                 /* Program the board's subsystem id/classcode */
 604                 pci_write_config_word(0, PCI_SUBSYSTEM_ID,
 605                                       CFG_PCI_SUBSYS_ID_NONMONARCH);
 606                 pci_write_config_word(0, PCI_CLASS_SUB_CODE,
 607                                       CFG_PCI_CLASSCODE_NONMONARCH);
 608
 609                 /* PCI configuration done: release ERREADY */
 610                 out_be32((void*)GPIO1_OR,
 611                          in_be32((void*)GPIO1_OR) | GPIO1_PPC_EREADY);
 612                 out_be32((void*)GPIO1_TCR,
 613                          in_be32((void*)GPIO1_TCR) | GPIO1_PPC_EREADY);
 614         } else {
 615                 /* Program the board's subsystem id/classcode */
 616                 pci_write_config_word(0, PCI_SUBSYSTEM_ID,
 617                                       CFG_PCI_SUBSYS_ID_MONARCH);
 618                 pci_write_config_word(0, PCI_CLASS_SUB_CODE,
 619                                       CFG_PCI_CLASSCODE_MONARCH);
 620         }
 621 }
 622 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
 623
 624 /*************************************************************************
 625  *  pci_master_init
 626  *
 627  ************************************************************************/
 628 #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
 629 void pci_master_init(struct pci_controller *hose)
 630 {
 631         unsigned short temp_short;
 632
 633         /*--------------------------------------------------------------------------+
 634           | Write the PowerPC440 EP PCI Configuration regs.
 635           |   Enable PowerPC440 EP to be a master on the PCI bus (PMM).
 636           |   Enable PowerPC440 EP to act as a PCI memory target (PTM).
 637           +--------------------------------------------------------------------------*/
 638         if (is_monarch()) {
 639                 pci_read_config_word(0, PCI_COMMAND, &temp_short);
 640                 pci_write_config_word(0, PCI_COMMAND,
 641                                       temp_short | PCI_COMMAND_MASTER |
 642                                       PCI_COMMAND_MEMORY);
 643         }
 644 }
 645 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
 646
 647
 648 static void wait_for_pci_ready(void)
 649 {
 650         int i;
 651         char *s = getenv("pcidelay");
 652         if (s) {
 653                 int ms = simple_strtoul(s, NULL, 10);
 654                 printf("PCI:   Waiting for %d ms\n", ms);
 655                 for (i=0; i<ms; i++)
 656                         udelay(1000);
 657         }
 658
 659         if (!(in_be32((void*)GPIO1_IR) & GPIO1_PPC_EREADY)) {
 660                 printf("PCI:   Waiting for EREADY (CTRL-C to skip) ... ");
 661                 while (1) {
 662                         if (ctrlc()) {
 663                                 puts("abort\n");
 664                                 break;
 665                         }
 666                         if (in_be32((void*)GPIO1_IR) & GPIO1_PPC_EREADY) {
 667                                 printf("done\n");
 668                                 break;
 669                         }
 670                 }
 671         }
 672 }
 673
 674
 675 /*************************************************************************
 676  *  is_pci_host
 677  *
 678  *      This routine is called to determine if a pci scan should be
 679  *      performed. With various hardware environments (especially cPCI and
 680  *      PPMC) it's insufficient to depend on the state of the arbiter enable
 681  *      bit in the strap register, or generic host/adapter assumptions.
 682  *
 683  *      Rather than hard-code a bad assumption in the general 440 code, the
 684  *      440 pci code requires the board to decide at runtime.
 685  *
 686  *      Return 0 for adapter mode, non-zero for host (monarch) mode.
 687  *
 688  *
 689  ************************************************************************/
 690 #if defined(CONFIG_PCI)
 691 int is_pci_host(struct pci_controller *hose)
 692 {
 693         char *s = getenv("pciscan");
 694         if (s == NULL)
 695                 if (is_monarch()) {
 696                         wait_for_pci_ready();
 697                         return 1;
 698                 } else
 699                         return 0;
 700         else if (!strcmp(s, "yes"))
 701                 return 1;
 702
 703         return 0;
 704 }
 705 #endif /* defined(CONFIG_PCI) */
 706 #if defined(CONFIG_POST)
 707 /*
 708  * Returns 1 if keys pressed to start the power-on long-running tests
 709  * Called from board_init_f().
 710  */
 711 int post_hotkeys_pressed(void)
 712 {
 713         return 0;       /* No hotkeys supported */
 714 }
 715 #endif /* CONFIG_POST */
 716
 717
 718 #ifdef CONFIG_RESET_PHY_R
 719 void reset_phy(void)
 720 {
 721         if (miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0001) == 0) {
 722                 miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, 0x0010);
 723                 miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, 0x0df0);
 724                 miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, 0x0e10);
 725                 miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0000);
 726         }
 727
 728         if (miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0001) == 0) {
 729                 miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, 0x0010);
 730                 miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, 0x0df0);
 731                 miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x10, 0x0e10);
 732                 miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0000);
 733         }
 734 }
 735 #endif
 736
 737 #if defined(CFG_EEPROM_WREN)
 738 /* Input: <dev_addr>  I2C address of EEPROM device to enable.
 739  *         <state>     -1: deliver current state
 740  *                     0: disable write
 741  *                     1: enable write
 742  *  Returns:           -1: wrong device address
 743  *                      0: dis-/en- able done
 744  *                   0/1: current state if <state> was -1.
 745  */
 746 int eeprom_write_enable(unsigned dev_addr, int state)
 747 {
 748         if ((CFG_I2C_EEPROM_ADDR != dev_addr) && (CFG_I2C_BOOT_EEPROM_ADDR != dev_addr)) {
 749                 return -1;
 750         } else {
 751                 switch (state) {
 752                 case 1:
 753                         /* Enable write access, clear bit GPIO_SINT2. */
 754                         out32(GPIO0_OR, in32(GPIO0_OR) & ~GPIO0_EP_EEP);
 755                         state = 0;
 756                         break;
 757                 case 0:
 758                         /* Disable write access, set bit GPIO_SINT2. */
 759                         out32(GPIO0_OR, in32(GPIO0_OR) | GPIO0_EP_EEP);
 760                         state = 0;
 761                         break;
 762                 default:
 763                         /* Read current status back. */
 764                         state = (0 == (in32(GPIO0_OR) & GPIO0_EP_EEP));
 765                         break;
 766                 }
 767         }
 768         return state;
 769 }
 770 #endif /* #if defined(CFG_EEPROM_WREN) */
 771
 772
 773 #define CFG_BOOT_EEPROM_PAGE_WRITE_BITS 3
 774 int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt)
 775 {
 776         unsigned end = offset + cnt;
 777         unsigned blk_off;
 778         int rcode = 0;
 779
 780 #if defined(CFG_EEPROM_WREN)
 781         eeprom_write_enable(dev_addr, 1);
 782 #endif
 783         /* Write data until done or would cross a write page boundary.
 784          * We must write the address again when changing pages
 785          * because the address counter only increments within a page.
 786          */
 787
 788         while (offset < end) {
 789                 unsigned alen, len;
 790                 unsigned maxlen;
 791                 uchar addr[2];
 792
 793                 blk_off = offset & 0xFF;        /* block offset */
 794
 795                 addr[0] = offset >> 8;          /* block number */
 796                 addr[1] = blk_off;              /* block offset */
 797                 alen    = 2;
 798                 addr[0] |= dev_addr;            /* insert device address */
 799
 800                 len = end - offset;
 801
 802 #define BOOT_EEPROM_PAGE_SIZE      (1 << CFG_BOOT_EEPROM_PAGE_WRITE_BITS)
 803 #define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1))
 804
 805                 maxlen = BOOT_EEPROM_PAGE_SIZE - BOOT_EEPROM_PAGE_OFFSET(blk_off);
 806                 if (maxlen > I2C_RXTX_LEN)
 807                         maxlen = I2C_RXTX_LEN;
 808
 809                 if (len > maxlen)
 810                         len = maxlen;
 811
 812                 if (i2c_write (addr[0], offset, alen-1, buffer, len) != 0)
 813                         rcode = 1;
 814
 815                 buffer += len;
 816                 offset += len;
 817
 818 #if defined(CFG_EEPROM_PAGE_WRITE_DELAY_MS)
 819                 udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
 820 #endif
 821         }
 822 #if defined(CFG_EEPROM_WREN)
 823         eeprom_write_enable(dev_addr, 0);
 824 #endif
 825         return rcode;
 826 }
 827
 828
 829 int bootstrap_eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt)
 830 {
 831         unsigned end = offset + cnt;
 832         unsigned blk_off;
 833         int rcode = 0;
 834
 835         /* Read data until done or would cross a page boundary.
 836          * We must write the address again when changing pages
 837          * because the next page may be in a different device.
 838          */
 839         while (offset < end) {
 840                 unsigned alen, len;
 841                 unsigned maxlen;
 842                 uchar addr[2];
 843
 844                 blk_off = offset & 0xFF;        /* block offset */
 845
 846                 addr[0] = offset >> 8;          /* block number */
 847                 addr[1] = blk_off;              /* block offset */
 848                 alen    = 2;
 849
 850                 addr[0] |= dev_addr;            /* insert device address */
 851
 852                 len = end - offset;
 853
 854                 maxlen = 0x100 - blk_off;
 855                 if (maxlen > I2C_RXTX_LEN)
 856                         maxlen = I2C_RXTX_LEN;
 857                 if (len > maxlen)
 858                         len = maxlen;
 859
 860                 if (i2c_read (addr[0], offset, alen-1, buffer, len) != 0)
 861                         rcode = 1;
 862                 buffer += len;
 863                 offset += len;
 864         }
 865
 866         return rcode;
 867 }
 868
 869
 870 #if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_BOARD_INIT)
 871 int usb_board_init(void)
 872 {
 873         char *act = getenv("usbact");
 874         int i;
 875
 876         if ((act == NULL || strcmp(act, "hostdev") == 0) &&
 877             !(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT))
 878                 /* enable power on USB socket */
 879                 out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_USB_PWR_N);
 880
 881         for (i=0; i<1000; i++)
 882                 udelay(1000);
 883
 884         return 0;
 885 }
 886
 887 int usb_board_stop(void)
 888 {
 889         /* disable power on USB socket */
 890         out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_USB_PWR_N);
 891         return 0;
 892 }
 893
 894 int usb_board_init_fail(void)
 895 {
 896         usb_board_stop();
 897         return 0;
 898 }
 899 #endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_BOARD_INIT) */
 900
 901 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 902 void ft_board_setup(void *blob, bd_t *bd)
 903 {
 904         u32 val[4];
 905         int rc;
 906
 907         ft_cpu_setup(blob, bd);
 908
 909         /* Fixup NOR mapping */
 910         val[0] = 0;                             /* chip select number */
 911         val[1] = 0;                             /* always 0 */
 912         val[2] = gd->bd->bi_flashstart;
 913         val[3] = gd->bd->bi_flashsize;
 914         rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
 915                                   val, sizeof(val), 1);
 916         if (rc)
 917                 printf("Unable to update property NOR mapping, err=%s\n",
 918                        fdt_strerror(rc));
 919 }
 920 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */