2 * (Cg) Copyright 2007-2008
3 * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
4 * Based on board/amcc/sequoia/sequoia.c
7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
10 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
11 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <fdt_support.h>
33 #include <asm/processor.h>
35 #include <asm/bitops.h>
38 #ifdef CONFIG_RESET_PHY_R
45 DECLARE_GLOBAL_DATA_PTR;
47 extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
48 extern void __ft_board_setup(void *blob, bd_t *bd);
50 ulong flash_get_size(ulong base, int banknum);
51 int pci_is_66mhz(void);
53 int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset,
54 uchar *buffer, unsigned cnt);
56 struct serial_device *default_serial_console(void)
64 * Use default console on P4 when strapping jumper
65 * is installed (bootstrap option != 'H').
67 mfsdr(SDR0_PINSTP, val);
68 if (((val & 0xf0000000) >> 29) != 7)
69 return &serial1_device;
71 ulong scratchreg = in_be32((void*)GPIO0_ISR3L);
72 if (!(scratchreg & 0x80)) {
73 /* mark scratchreg valid */
74 scratchreg = (scratchreg & 0xffffff00) | 0x80;
76 i = bootstrap_eeprom_read(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR,
78 if ((i != -1) && (buf[0] == 0x19) && (buf[1] == 0x75)) {
81 /* bringup delay for console */
82 for (delay=0; delay<(1000 * (ulong)buf[3]); delay++) {
87 out_be32((void*)GPIO0_ISR3L, scratchreg);
90 if (scratchreg & 0x01)
91 return &serial1_device;
93 return &serial0_device;
96 int board_early_init_f(void)
99 u32 sdr0_pfc1, sdr0_pfc2;
102 /* general EBC configuration (disable EBC timeouts) */
103 mtdcr(EBC0_CFGADDR, EBC0_CFG);
104 mtdcr(EBC0_CFGDATA, 0xf8400000);
107 * Setup the GPIO pins
108 * TODO: setup GPIOs via CONFIG_SYS_4xx_GPIO_TABLE in board's config file
110 out_be32((void *)GPIO0_OR, 0x40000102);
111 out_be32((void *)GPIO0_TCR, 0x4c90011f);
112 out_be32((void *)GPIO0_OSRL, 0x28051400);
113 out_be32((void *)GPIO0_OSRH, 0x55005000);
114 out_be32((void *)GPIO0_TSRL, 0x08051400);
115 out_be32((void *)GPIO0_TSRH, 0x55005000);
116 out_be32((void *)GPIO0_ISR1L, 0x54000000);
117 out_be32((void *)GPIO0_ISR1H, 0x00000000);
118 out_be32((void *)GPIO0_ISR2L, 0x44000000);
119 out_be32((void *)GPIO0_ISR2H, 0x00000100);
120 out_be32((void *)GPIO0_ISR3L, 0x00000000);
121 out_be32((void *)GPIO0_ISR3H, 0x00000000);
123 out_be32((void *)GPIO1_OR, 0x80002408);
124 out_be32((void *)GPIO1_TCR, 0xd6003c08);
125 out_be32((void *)GPIO1_OSRL, 0x0a5a0000);
126 out_be32((void *)GPIO1_OSRH, 0x00000000);
127 out_be32((void *)GPIO1_TSRL, 0x00000000);
128 out_be32((void *)GPIO1_TSRH, 0x00000000);
129 out_be32((void *)GPIO1_ISR1L, 0x00005555);
130 out_be32((void *)GPIO1_ISR1H, 0x40000000);
131 out_be32((void *)GPIO1_ISR2L, 0x04010000);
132 out_be32((void *)GPIO1_ISR2H, 0x00000000);
133 out_be32((void *)GPIO1_ISR3L, 0x01400000);
134 out_be32((void *)GPIO1_ISR3H, 0x00000000);
136 /* patch PLB:PCI divider for 66MHz PCI */
137 mfcpr(CPR0_SPCID, reg);
138 if (pci_is_66mhz() && (reg != 0x02000000)) {
139 mtcpr(CPR0_SPCID, 0x02000000); /* 133MHZ : 2 for 66MHz PCI */
141 mfcpr(CPR0_ICFG, reg);
142 reg |= CPR0_ICFG_RLI_MASK;
143 mtcpr(CPR0_ICFG, reg);
145 mtspr(SPRN_DBCR0, 0x20000000); /* do chip reset */
149 * Setup the interrupt controller polarities, triggers, etc.
151 mtdcr(UIC0SR, 0xffffffff); /* clear all */
152 mtdcr(UIC0ER, 0x00000000); /* disable all */
153 mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
154 mtdcr(UIC0PR, 0xfffff7ef);
155 mtdcr(UIC0TR, 0x00000000);
156 mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
157 mtdcr(UIC0SR, 0xffffffff); /* clear all */
159 mtdcr(UIC1SR, 0xffffffff); /* clear all */
160 mtdcr(UIC1ER, 0x00000000); /* disable all */
161 mtdcr(UIC1CR, 0x00000000); /* all non-critical */
162 mtdcr(UIC1PR, 0xffffc7f5);
163 mtdcr(UIC1TR, 0x00000000);
164 mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
165 mtdcr(UIC1SR, 0xffffffff); /* clear all */
167 mtdcr(UIC2SR, 0xffffffff); /* clear all */
168 mtdcr(UIC2ER, 0x00000000); /* disable all */
169 mtdcr(UIC2CR, 0x00000000); /* all non-critical */
170 mtdcr(UIC2PR, 0x27ffffff);
171 mtdcr(UIC2TR, 0x00000000);
172 mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
173 mtdcr(UIC2SR, 0xffffffff); /* clear all */
175 /* select Ethernet pins */
176 mfsdr(SDR0_PFC1, sdr0_pfc1);
177 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
178 SDR0_PFC1_SELECT_CONFIG_4;
179 mfsdr(SDR0_PFC2, sdr0_pfc2);
180 sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
181 SDR0_PFC2_SELECT_CONFIG_4;
184 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
186 mtsdr(SDR0_PFC2, sdr0_pfc2);
187 mtsdr(SDR0_PFC1, sdr0_pfc1);
189 /* setup NAND FLASH */
190 mfsdr(SDR0_CUST0, sdr0_cust0);
191 sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
192 SDR0_CUST0_NDFC_ENABLE |
193 SDR0_CUST0_NDFC_BW_8_BIT |
194 SDR0_CUST0_NDFC_ARE_MASK |
195 (0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
196 mtsdr(SDR0_CUST0, sdr0_cust0);
201 #if defined(CONFIG_MISC_INIT_F)
202 int misc_init_f(void)
204 struct pci_controller hose;
205 hose.first_busno = 0;
207 hose.region_count = 0;
209 if (getenv("pciearly") && (!is_monarch())) {
210 printf("PCI: early target init\n");
211 pci_setup_indirect(&hose, PCIL0_CFGADR, PCIL0_CFGDATA);
212 pci_target_init(&hose);
221 int misc_init_r(void)
226 unsigned long usb2d0cr = 0;
227 unsigned long usb2phy0cr, usb2h0cr = 0;
228 unsigned long sdr0_pfc1;
229 unsigned long sdr0_srst0, sdr0_srst1;
230 char *act = getenv("usbact");
236 /* Re-do sizing to get full correct info */
238 /* adjust flash start and offset */
239 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
240 gd->bd->bi_flashoffset = 0;
242 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
243 mtdcr(EBC0_CFGADDR, PB2CR);
245 mtdcr(EBC0_CFGADDR, PB0CR);
247 pbcr = mfdcr(EBC0_CFGDATA);
248 size_val = ffs(gd->bd->bi_flashsize) - 21;
249 pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
250 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
251 mtdcr(EBC0_CFGADDR, PB2CR);
253 mtdcr(EBC0_CFGADDR, PB0CR);
255 mtdcr(EBC0_CFGDATA, pbcr);
258 * Re-check to get correct base address
260 flash_get_size(gd->bd->bi_flashstart, 0);
262 #ifdef CONFIG_ENV_IS_IN_FLASH
263 /* Monitor protection ON by default */
264 (void)flash_protect(FLAG_PROTECT_SET,
265 -CONFIG_SYS_MONITOR_LEN,
269 /* Env protection ON by default */
270 (void)flash_protect(FLAG_PROTECT_SET,
271 CONFIG_ENV_ADDR_REDUND,
272 CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
279 if ((act == NULL || strcmp(act, "host") == 0) &&
280 !(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)){
282 mfsdr(SDR0_PFC1, sdr0_pfc1);
283 mfsdr(SDR0_USB2D0CR, usb2d0cr);
284 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
285 mfsdr(SDR0_USB2H0CR, usb2h0cr);
287 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
288 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
289 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
290 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
291 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
292 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
293 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
294 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
295 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
296 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
299 * An 8-bit/60MHz interface is the only possible alternative
300 * when connecting the Device to the PHY
302 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
303 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
305 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
306 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
308 mtsdr(SDR0_PFC1, sdr0_pfc1);
309 mtsdr(SDR0_USB2D0CR, usb2d0cr);
310 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
311 mtsdr(SDR0_USB2H0CR, usb2h0cr);
314 * Take USB out of reset:
315 * -Initial status = all cores are in reset
316 * -deassert reset to OPB1, P4OPB0, OPB2, PLB42OPB1 OPB2PLB40 cores
318 * -deassert reset to PHY
320 * -deassert reset to HOST
322 * -deassert all other resets
324 mfsdr(SDR0_SRST1, sdr0_srst1);
325 sdr0_srst1 &= ~(SDR0_SRST1_OPBA1 | \
326 SDR0_SRST1_P4OPB0 | \
328 SDR0_SRST1_PLB42OPB1 | \
329 SDR0_SRST1_OPB2PLB40);
330 mtsdr(SDR0_SRST1, sdr0_srst1);
333 mfsdr(SDR0_SRST1, sdr0_srst1);
334 sdr0_srst1 &= ~SDR0_SRST1_USB20PHY;
335 mtsdr(SDR0_SRST1, sdr0_srst1);
338 mfsdr(SDR0_SRST0, sdr0_srst0);
339 sdr0_srst0 &= ~SDR0_SRST0_USB2H;
340 mtsdr(SDR0_SRST0, sdr0_srst0);
343 /* finally all the other resets */
344 mtsdr(SDR0_SRST1, 0x00000000);
345 mtsdr(SDR0_SRST0, 0x00000000);
347 if (!(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) {
348 /* enable power on USB socket */
349 out_be32((void*)GPIO1_OR,
350 in_be32((void*)GPIO1_OR) & ~GPIO1_USB_PWR_N);
353 printf("USB: Host\n");
355 } else if ((strcmp(act, "dev") == 0) ||
356 (in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) {
357 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
359 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
360 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
361 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
362 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
363 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
364 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
365 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
366 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
367 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
370 mtsdr(SDR0_SRST1, 0x672c6000);
373 mtsdr(SDR0_SRST0, 0x00000080);
376 mtsdr(SDR0_SRST1, 0x60206000);
378 *(unsigned int *)(0xe0000350) = 0x00000001;
381 mtsdr(SDR0_SRST1, 0x60306000);
384 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
385 mfsdr(SDR0_USB2H0CR, usb2h0cr);
386 mfsdr(SDR0_USB2D0CR, usb2d0cr);
387 mfsdr(SDR0_PFC1, sdr0_pfc1);
389 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
390 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
391 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
392 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
393 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
394 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
395 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
396 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
397 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
398 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
400 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
401 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
403 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
405 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
406 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
408 mtsdr(SDR0_USB2H0CR, usb2h0cr);
409 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
410 mtsdr(SDR0_USB2D0CR, usb2d0cr);
411 mtsdr(SDR0_PFC1, sdr0_pfc1);
415 mtsdr(SDR0_SRST1, 0x00000000);
417 mtsdr(SDR0_SRST0, 0x00000000);
419 printf("USB: Device\n");
423 * Clear PLB4A0_ACR[WRP]
424 * This fix will make the MAL burst disabling patch for the Linux
425 * EMAC driver obsolete.
427 reg = mfdcr(PLB4_ACR) & ~PLB4_ACR_WRP;
428 mtdcr(PLB4_ACR, reg);
434 /* turn off POST LED */
435 out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_POST_N);
436 /* turn on RUN LED */
437 out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~GPIO0_LED_RUN_N);
443 if (in_be32((void*)GPIO1_IR) & GPIO1_NONMONARCH)
449 int pci_is_66mhz(void)
451 if (in_be32((void*)GPIO1_IR) & GPIO1_M66EN)
456 int board_revision(void)
458 return (int)((in_be32((void*)GPIO1_IR) & GPIO1_HWID_MASK) >> 4);
463 puts("Board: esd GmbH - PMC440");
465 gd->board_type = board_revision();
466 printf(", Rev 1.%ld, ", gd->board_type);
472 printf("monarch, PCI=%s MHz\n", pci_is_66mhz() ? "66" : "33");
477 #if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
479 * Assign interrupts to PCI devices. Some OSs rely on this.
481 void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
483 unsigned char int_line[] = {IRQ_PCIC, IRQ_PCID, IRQ_PCIA, IRQ_PCIB};
485 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
486 int_line[PCI_DEV(dev) & 0x03]);
493 * The bootstrap configuration provides default settings for the pci
494 * inbound map (PIM). But the bootstrap config choices are limited and
495 * may not be sufficient for a given board.
497 #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
498 void pci_target_init(struct pci_controller *hose)
500 char *ptmla_str, *ptmms_str;
503 * Set up Direct MMIO registers
506 * PowerPC440EPX PCI Master configuration.
507 * Map one 1Gig range of PLB/processor addresses to PCI memory space.
508 * PLB address 0x80000000-0xBFFFFFFF
509 * ==> PCI address 0x80000000-0xBFFFFFFF
510 * Use byte reversed out routines to handle endianess.
511 * Make this region non-prefetchable.
513 out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
514 /* - disabled b4 setting */
515 out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
516 out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
517 out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
518 out32r(PCIL0_PMM0MA, 0xc0000001); /* 1G + No prefetching, */
519 /* and enable region */
522 ptmla_str = getenv("ptm1la");
523 ptmms_str = getenv("ptm1ms");
524 if(NULL != ptmla_str && NULL != ptmms_str ) {
526 simple_strtoul(ptmms_str, NULL, 16));
528 simple_strtoul(ptmla_str, NULL, 16));
530 /* BAR1: default top 64MB of RAM */
531 out32r(PCIL0_PTM1MS, 0xfc000001);
532 out32r(PCIL0_PTM1LA, 0x0c000000);
535 /* BAR1: default: complete 256MB RAM */
536 out32r(PCIL0_PTM1MS, 0xf0000001);
537 out32r(PCIL0_PTM1LA, 0x00000000);
540 ptmla_str = getenv("ptm2la"); /* Local Addr. Reg */
541 ptmms_str = getenv("ptm2ms"); /* Memory Size/Attribute */
542 if(NULL != ptmla_str && NULL != ptmms_str ) {
543 out32r(PCIL0_PTM2MS, simple_strtoul(ptmms_str, NULL, 16));
544 out32r(PCIL0_PTM2LA, simple_strtoul(ptmla_str, NULL, 16));
546 /* BAR2: default: 4MB FPGA */
547 out32r(PCIL0_PTM2MS, 0xffc00001); /* Memory Size/Attribute */
548 out32r(PCIL0_PTM2LA, 0xef000000); /* Local Addr. Reg */
552 /* BAR2: map FPGA registers behind system memory at 1GB */
553 pci_hose_write_config_dword(hose, 0, PCI_BASE_ADDRESS_2, 0x40000008);
557 * Set up Configuration registers
560 /* Program the board's vendor id */
561 pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_VENDOR_ID,
562 CONFIG_SYS_PCI_SUBSYS_VENDORID);
564 /* disabled for PMC405 backward compatibility */
565 /* Configure command register as bus master */
566 /* pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); */
569 /* 240nS PCI clock */
570 pci_hose_write_config_word(hose, 0, PCI_LATENCY_TIMER, 1);
572 /* No error reporting */
573 pci_hose_write_config_word(hose, 0, PCI_ERREN, 0);
575 pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
578 /* Program the board's subsystem id/classcode */
579 pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID,
580 CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH);
581 pci_hose_write_config_word(hose, 0, PCI_CLASS_SUB_CODE,
582 CONFIG_SYS_PCI_CLASSCODE_NONMONARCH);
584 /* PCI configuration done: release ERREADY */
585 out_be32((void*)GPIO1_OR,
586 in_be32((void*)GPIO1_OR) | GPIO1_PPC_EREADY);
587 out_be32((void*)GPIO1_TCR,
588 in_be32((void*)GPIO1_TCR) | GPIO1_PPC_EREADY);
590 /* Program the board's subsystem id/classcode */
591 pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID,
592 CONFIG_SYS_PCI_SUBSYS_ID_MONARCH);
593 pci_hose_write_config_word(hose, 0, PCI_CLASS_SUB_CODE,
594 CONFIG_SYS_PCI_CLASSCODE_MONARCH);
597 /* enable host configuration */
598 pci_hose_write_config_dword(hose, 0, PCI_BRDGOPT2, 0x00000101);
600 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
605 #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
606 void pci_master_init(struct pci_controller *hose)
608 unsigned short temp_short;
611 * Write the PowerPC440 EP PCI Configuration regs.
612 * Enable PowerPC440 EP to be a master on the PCI bus (PMM).
613 * Enable PowerPC440 EP to act as a PCI memory target (PTM).
616 pci_read_config_word(0, PCI_COMMAND, &temp_short);
617 pci_write_config_word(0, PCI_COMMAND,
618 temp_short | PCI_COMMAND_MASTER |
622 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
624 static void wait_for_pci_ready(void)
627 char *s = getenv("pcidelay");
629 * We have our own handling of the pcidelay variable.
630 * Using CONFIG_PCI_BOOTDELAY enables pausing for host
631 * and adapter devices. For adapter devices we do not
635 int ms = simple_strtoul(s, NULL, 10);
636 printf("PCI: Waiting for %d ms\n", ms);
641 if (!(in_be32((void*)GPIO1_IR) & GPIO1_PPC_EREADY)) {
642 printf("PCI: Waiting for EREADY (CTRL-C to skip) ... ");
648 if (in_be32((void*)GPIO1_IR) & GPIO1_PPC_EREADY) {
657 * Override weak is_pci_host()
659 * This routine is called to determine if a pci scan should be
660 * performed. With various hardware environments (especially cPCI and
661 * PPMC) it's insufficient to depend on the state of the arbiter enable
662 * bit in the strap register, or generic host/adapter assumptions.
664 * Rather than hard-code a bad assumption in the general 440 code, the
665 * 440 pci code requires the board to decide at runtime.
667 * Return 0 for adapter mode, non-zero for host (monarch) mode.
669 #if defined(CONFIG_PCI)
670 int is_pci_host(struct pci_controller *hose)
672 char *s = getenv("pciscan");
675 wait_for_pci_ready();
679 else if (!strcmp(s, "yes"))
684 #endif /* defined(CONFIG_PCI) */
686 #if defined(CONFIG_POST)
688 * Returns 1 if keys pressed to start the power-on long-running tests
689 * Called from board_init_f().
691 int post_hotkeys_pressed(void)
693 return 0; /* No hotkeys supported */
695 #endif /* CONFIG_POST */
697 #ifdef CONFIG_RESET_PHY_R
701 unsigned short val_method, val_behavior;
703 /* special LED setup for NGCC/CANDES */
704 if ((s = getenv("bd_type")) &&
705 ((!strcmp(s, "ngcc")) || (!strcmp(s, "candes")))) {
707 val_behavior = 0x0cf2;
709 /* PMC440 standard type */
711 val_behavior = 0x0cf0;
714 if (miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0001) == 0) {
715 miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, 0x0010);
716 miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, val_behavior);
717 miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, val_method);
718 miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0000);
721 if (miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0001) == 0) {
722 miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, 0x0010);
723 miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, val_behavior);
724 miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x10, val_method);
725 miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0000);
730 #if defined(CONFIG_SYS_EEPROM_WREN)
732 * Input: <dev_addr> I2C address of EEPROM device to enable.
733 * <state> -1: deliver current state
736 * Returns: -1: wrong device address
737 * 0: dis-/en- able done
738 * 0/1: current state if <state> was -1.
740 int eeprom_write_enable(unsigned dev_addr, int state)
742 if ((CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) &&
743 (CONFIG_SYS_I2C_BOOT_EEPROM_ADDR != dev_addr)) {
748 /* Enable write access, clear bit GPIO_SINT2. */
749 out_be32((void *)GPIO0_OR,
750 in_be32((void *)GPIO0_OR) & ~GPIO0_EP_EEP);
754 /* Disable write access, set bit GPIO_SINT2. */
755 out_be32((void *)GPIO0_OR,
756 in_be32((void *)GPIO0_OR) | GPIO0_EP_EEP);
760 /* Read current status back. */
761 state = (0 == (in_be32((void *)GPIO0_OR)
768 #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
770 #define CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS 3
771 int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset,
772 uchar *buffer, unsigned cnt)
774 unsigned end = offset + cnt;
778 #if defined(CONFIG_SYS_EEPROM_WREN)
779 eeprom_write_enable(dev_addr, 1);
782 * Write data until done or would cross a write page boundary.
783 * We must write the address again when changing pages
784 * because the address counter only increments within a page.
787 while (offset < end) {
792 blk_off = offset & 0xFF; /* block offset */
794 addr[0] = offset >> 8; /* block number */
795 addr[1] = blk_off; /* block offset */
797 addr[0] |= dev_addr; /* insert device address */
801 #define BOOT_EEPROM_PAGE_SIZE (1 << CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS)
802 #define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1))
804 maxlen = BOOT_EEPROM_PAGE_SIZE -
805 BOOT_EEPROM_PAGE_OFFSET(blk_off);
806 if (maxlen > I2C_RXTX_LEN)
807 maxlen = I2C_RXTX_LEN;
812 if (i2c_write (addr[0], offset, alen-1, buffer, len) != 0)
818 #if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
819 udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
822 #if defined(CONFIG_SYS_EEPROM_WREN)
823 eeprom_write_enable(dev_addr, 0);
828 int bootstrap_eeprom_read (unsigned dev_addr, unsigned offset,
829 uchar *buffer, unsigned cnt)
831 unsigned end = offset + cnt;
836 * Read data until done or would cross a page boundary.
837 * We must write the address again when changing pages
838 * because the next page may be in a different device.
840 while (offset < end) {
845 blk_off = offset & 0xFF; /* block offset */
847 addr[0] = offset >> 8; /* block number */
848 addr[1] = blk_off; /* block offset */
851 addr[0] |= dev_addr; /* insert device address */
855 maxlen = 0x100 - blk_off;
856 if (maxlen > I2C_RXTX_LEN)
857 maxlen = I2C_RXTX_LEN;
861 if (i2c_read (addr[0], offset, alen-1, buffer, len) != 0)
870 #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
871 int usb_board_init(void)
873 char *act = getenv("usbact");
876 if ((act == NULL || strcmp(act, "host") == 0) &&
877 !(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT))
878 /* enable power on USB socket */
879 out_be32((void*)GPIO1_OR,
880 in_be32((void*)GPIO1_OR) & ~GPIO1_USB_PWR_N);
882 for (i=0; i<1000; i++)
888 int usb_board_stop(void)
890 /* disable power on USB socket */
891 out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_USB_PWR_N);
895 int usb_board_init_fail(void)
900 #endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */
902 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
903 void ft_board_setup(void *blob, bd_t *bd)
907 __ft_board_setup(blob, bd);
910 * Disable PCI in non-monarch mode.
913 rc = fdt_find_and_setprop(blob, "/plb/pci@1ec000000", "status",
914 "disabled", sizeof("disabled"), 1);
916 printf("Unable to update property status in PCI node, err=%s\n",
921 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */