2 * SPDX-License-Identifier: GPL-2.0+
5 #include <asm-offsets.h>
6 #include <ppc_asm.tmpl>
13 * This table is used by the cpu boot code to setup the initial tlb
14 * entries. Rather than make broad assumptions in the cpu source tree,
15 * this table lets each board set things up however they like.
17 * Pointer to the table is returned in r1
27 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
28 * speed up boot process. It is patched after relocation to enable SA_I
30 #ifndef CONFIG_NAND_SPL
31 tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G )
33 tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_RWX | SA_G )
36 /* TLB entries for DDR2 SDRAM are generated dynamically */
38 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
39 /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
40 tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G )
43 /* TLB-entry for PCI Memory */
44 tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG )
45 tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG )
46 tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG )
47 tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG )
49 /* TLB-entries for EBC */
50 /* PMC440 maps EBC to 0xef000000 which is handled by the peripheral
52 * This dummy entry is only for convinience in order not to modify the
53 * amount of entries. Currently OS/9 relies on this :-)
55 tlbentry( 0xc0000000, SZ_256M, 0xc0000000, 1, AC_RWX | SA_IG )
57 /* TLB-entry for NAND */
58 tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_RWX | SA_IG )
60 /* TLB-entry for Internal Registers & OCM */
61 tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_RWX | SA_I )
63 /*TLB-entry PCI registers*/
64 tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG )
66 /* TLB-entry for peripherals */
67 tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
69 /* TLB-entry PCI IO space */
70 tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RWX | SA_IG)
72 /* TODO: what about high IO space */
75 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
77 * For NAND booting the first TLB has to be reconfigured to full size
78 * and with caching disabled after running from RAM!
80 #define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
81 #define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1)
82 #define TLB02 TLB2(AC_RWX | SA_IG)
88 addi r4,r0,0x0000 /* TLB entry #0 */
91 tlbwe r5,r4,0x0000 /* Save it out */
94 tlbwe r5,r4,0x0001 /* Save it out */
97 tlbwe r5,r4,0x0002 /* Save it out */