2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian@popies.net>
4 * Lead Tech Design <www.leadtechdesign.com>
6 * (C) Copyright 2009-2015
7 * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
8 * esd electronic system design gmbh <www.esd.eu>
10 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/at91sam9_smc.h>
17 #include <asm/arch/at91_common.h>
18 #include <asm/arch/at91_pmc.h>
19 #include <asm/arch/at91_rstc.h>
20 #include <asm/arch/at91_matrix.h>
21 #include <asm/arch/at91_pio.h>
22 #include <asm/arch/clk.h>
25 DECLARE_GLOBAL_DATA_PTR;
28 * Miscelaneous platform dependent initialisations
31 #ifdef CONFIG_REVISION_TAG
32 static int hw_rev = -1; /* hardware revision */
39 hw_rev = at91_get_pio_value(AT91_PIO_PORTB, 19);
40 hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 20) << 1;
41 hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 21) << 2;
42 hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 22) << 3;
49 #endif /* CONFIG_REVISION_TAG */
51 #ifdef CONFIG_CMD_NAND
52 static void meesc_nand_hw_init(void)
55 at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0;
56 at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
59 csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
60 writel(csa, &matrix->csa[0]);
62 /* Configure SMC CS3 for NAND/SmartMedia */
63 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
64 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(2),
67 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
68 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
71 writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6),
73 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
74 AT91_SMC_MODE_EXNW_DISABLE |
76 AT91_SMC_MODE_TDF_CYCLE(12),
79 /* Configure RDY/BSY */
80 gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
82 /* Enable NandFlash */
83 gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
85 #endif /* CONFIG_CMD_NAND */
88 static void meesc_macb_hw_init(void)
90 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
92 writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
98 * Static memory controller initialization to enable Beckhoff ET1100 EtherCAT
99 * controller debugging
100 * The ET1100 is located at physical address 0x70000000
101 * Its process memory is located at physical address 0x70001000
103 static void meesc_ethercat_hw_init(void)
105 at91_smc_t *smc1 = (at91_smc_t *) ATMEL_BASE_SMC1;
107 /* Configure SMC EBI1_CS0 for EtherCAT */
108 writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
109 AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
111 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(9) |
112 AT91_SMC_PULSE_NRD(5) | AT91_SMC_PULSE_NCS_RD(9),
114 writel(AT91_SMC_CYCLE_NWE(10) | AT91_SMC_CYCLE_NRD(6),
117 * Configure behavior at external wait signal, byte-select mode, 16 bit
118 * data bus width, none data float wait states and TDF optimization
120 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_EXNW_READY |
121 AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_TDF_CYCLE(0) |
122 AT91_SMC_MODE_TDF, &smc1->cs[0].mode);
124 /* Configure RDY/BSY */
125 at91_set_b_periph(AT91_PIO_PORTE, 20, 0); /* EBI1_NWAIT */
130 /* dram_init must store complete ramsize in gd->ram_size */
131 gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
136 void dram_init_banksize(void)
138 gd->bd->bi_dram[0].start = PHYS_SDRAM;
139 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
142 int board_eth_init(bd_t *bis)
146 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
151 #ifdef CONFIG_DISPLAY_BOARDINFO
155 u_char hw_type; /* hardware type */
157 /* read the "Type" register of the ET1100 controller */
158 hw_type = readb(CONFIG_ET1100_BASE);
163 /* ET1100 present, arch number of MEESC-Board */
164 gd->bd->bi_arch_number = MACH_TYPE_MEESC;
165 puts("Board: CAN-EtherCAT Gateway");
168 /* no ET1100 present, arch number of EtherCAN/2-Board */
169 gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
170 puts("Board: EtherCAN/2 Gateway");
171 /* switch on LED1D */
172 at91_set_pio_output(AT91_PIO_PORTB, 12, 1);
175 /* assume, no ET1100 present, arch number of EtherCAN/2-Board */
176 gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
177 printf("ERROR! Read invalid hw_type: %02X\n", hw_type);
178 puts("Board: EtherCAN/2 Gateway");
181 if (getenv_f("serial#", str, sizeof(str)) > 0) {
185 #ifdef CONFIG_REVISION_TAG
186 printf("\nHardware-revision: 1.%d\n", get_hw_rev());
188 printf("Mach-type: %lu\n", gd->bd->bi_arch_number);
191 #endif /* CONFIG_DISPLAY_BOARDINFO */
193 #ifdef CONFIG_SERIAL_TAG
194 void get_board_serial(struct tag_serialnr *serialnr)
198 char *serial = getenv("serial#");
200 str = strchr(serial, '_');
201 if (str && (strlen(str) >= 4)) {
202 serialnr->high = (*(str + 1) << 8) | *(str + 2);
203 serialnr->low = simple_strtoul(str + 3, NULL, 16);
212 #ifdef CONFIG_REVISION_TAG
213 u32 get_board_rev(void)
215 return hw_rev | 0x100;
219 #ifdef CONFIG_MISC_INIT_R
220 int misc_init_r(void)
224 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
227 * Normally the processor clock has a divisor of 2.
228 * In some cases this this needs to be set to 4.
229 * Check the user has set environment mdiv to 4 to change the divisor.
231 if ((str = getenv("mdiv")) && (strcmp(str, "4") == 0)) {
232 writel((readl(&pmc->mckr) & ~AT91_PMC_MDIV) |
233 AT91SAM9_PMC_MDIV_4, &pmc->mckr);
234 at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
236 /* Notify the user that the clock is not default */
237 printf("Setting master clock to %s MHz\n",
238 strmhz(buf, get_mck_clk_rate()));
243 #endif /* CONFIG_MISC_INIT_R */
245 int board_early_init_f(void)
247 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
249 /* enable all clocks */
250 writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
251 (1 << ATMEL_ID_PIOCDE) | (1 << ATMEL_ID_UHP),
254 at91_seriald_hw_init();
261 /* initialize ET1100 Controller */
262 meesc_ethercat_hw_init();
264 /* adress of boot parameters */
265 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
267 #ifdef CONFIG_CMD_NAND
268 meesc_nand_hw_init();
270 #ifdef CONFIG_HAS_DATAFLASH
271 at91_spi0_hw_init(1 << 0);
274 meesc_macb_hw_init();
276 #ifdef CONFIG_AT91_CAN
279 #ifdef CONFIG_USB_OHCI_NEW